Patents by Inventor Ryoji Kosugi
Ryoji Kosugi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11282919Abstract: A semiconductor device that includes a SiC semiconductor substrate; a SiC epitaxial layer having an impurity concentration lower than that of the SiC semiconductor substrate; a first semiconductor layer including first semiconductor pillars and second semiconductor pillars; a second semiconductor layer; a device active region; a termination region; a channel stopper region having an impurity concentration higher than that of the SiC epitaxial layer; and a plurality of first chip end portions and a plurality of second chip end portions, and a surface of the first side surface is covered with an impurity region having an impurity concentration higher than those of the first semiconductor pillar and the SiC epitaxial layer and is connected to the channel stopper region.Type: GrantFiled: February 15, 2019Date of Patent: March 22, 2022Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, FUJI ELECTRIC CO., LTD., MITSUBISHI ELECTRIC CORPORATIONInventors: Ryoji Kosugi, Kazuhiro Mochizuki, Kohei Adachi, Manabu Takei, Yoshiyuki Yonezawa
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Publication number: 20210111245Abstract: A semiconductor device that includes a SiC semiconductor substrate; a SiC epitaxial layer having an impurity concentration lower than that of the SiC semiconductor substrate; a first semiconductor layer including first semiconductor pillars and second semiconductor pillars; a second semiconductor layer; a device active region; a termination region; a channel stopper region having an impurity concentration higher than that of the SiC epitaxial layer; and a plurality of first chip end portions and a plurality of second chip end portions, and a surface of the first side surface is covered with an impurity region having an impurity concentration higher than those of the first semiconductor pillar and the SiC epitaxial layer and is connected to the channel stopper region.Type: ApplicationFiled: February 15, 2019Publication date: April 15, 2021Applicants: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, FUJI ELECTRIC CO., LTD., Mitsubishi Electric CorporationInventors: Ryoji KOSUGI, Kazuhiro MOCHIZUKI, Kohei ADACHI, Manabu TAKEI, Yoshiyuki YONEZAWA
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Patent number: 10741648Abstract: A manufacturing yield and reliability of a semiconductor device including a power semiconductor element is improved. A plurality of trenches DT extending in an x direction and spaced apart from each other in a y direction orthogonal to the x direction are formed in a substrate having a main crystal surface tilted with respect to a <11-20> direction. Also, a super-junction structure is constituted of a p-type column region PC made of a semiconductor layer embedded in the trench DT and an n-type column region NC made of a part of the substrate between the trenches DT adjacent in the y direction, and an angle error between the extending direction of the trench DT (x direction) and the <11-20> direction is within ±?. The ? is determined by {arctan {k× (w/h)}}/13 for the trench having a height of h and a width of w. Herein, the k is at least smaller than 2, preferably 0.9 or less, more preferably 0.5 or less, and still more preferably 0.3 or less.Type: GrantFiled: June 2, 2017Date of Patent: August 11, 2020Assignees: National Institute of Advanced Industrial Science and Technology, Hitachi, Ltd, Fuji Electric Co., Ltd, Mitsubishi Electric CorporationInventors: Ryoji Kosugi, Shiyang Ji, Kazuhiro Mochizuki, Yasuyuki Kawada, Hidenori Kouketsu
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Publication number: 20190157399Abstract: A manufacturing yield and reliability of a semiconductor device including a power semiconductor element is improved. A plurality of trenches DT extending in an x direction and spaced apart from each other in a y direction orthogonal to the x direction are formed in a substrate having a main crystal surface tilted with respect to a <11-20> direction. Also, a super-junction structure is constituted of a p-type column region PC made of a semiconductor layer embedded in the trench DT and an n-type column region NC made of a part of the substrate between the trenches DT adjacent in the y direction, and an angle error between the extending direction of the trench DT (x direction) and the <11-20> direction is within ±?. The ? is determined by {arctan {k× (w/h)}}/13 for the trench having a height of h and a width of w. Herein, the k is at least smaller than 2, preferably 0.9 or less, more preferably 0.5 or less, and still more preferably 0.3 or less.Type: ApplicationFiled: June 2, 2017Publication date: May 23, 2019Inventors: Ryoji Kosugi, Shiyang Ji, Kazuhiro Mochizuki, Yasuyuki Kawda, Hidenori Kouketsu
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Patent number: 10186575Abstract: In a silicon carbide semiconductor device, an n-type drift layer is formed on a front surface of an n++-type semiconductor substrate. Next, a trench is formed in the n-type drift layer, from a surface of the n-type drift layer. Next, a p-type pillar region is formed in the trench. A depth of the trench is at least three times a width of the trench. The p-type pillar region is formed by concurrently introducing a p-type first dopant and a gas containing an n-type second dopant incorporated at an atom position different from that of the first dopant.Type: GrantFiled: February 23, 2018Date of Patent: January 22, 2019Assignees: FUJI ELECTRIC CO., LTD., MITSUBISHI ELECTRIC CORPORATIONInventors: Yasuyuki Kawada, Shiyang Ji, Ryoji Kosugi, Hidenori Koketsu, Kazuhiro Mochizuki
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Publication number: 20180248002Abstract: In a silicon carbide semiconductor device, an n-type drift layer is formed on a front surface of an n++-type semiconductor substrate. Next, a trench is formed in the n-type drift layer, from a surface of the n-type drift layer. Next, a p-type pillar region is formed in the trench. A depth of the trench is at least three times a width of the trench. The p-type pillar region is formed by concurrently introducing a p-type first dopant and a gas containing an n-type second dopant incorporated at an atom position different from that of the first dopant.Type: ApplicationFiled: February 23, 2018Publication date: August 30, 2018Applicants: FUJI ELECTRIC CO., LTD., MITSUBISHI ELECTRIC CORPORATIONInventors: Yasuyuki KAWADA, Shiyang JI, Ryoji KOSUGI, Hidenori KOKETSU, Kazuhiro MOCHIZUKI
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Patent number: 7538352Abstract: In a semiconductor device that uses a silicon carbide semiconductor substrate having p type, n type impurity semiconductor regions formed by ion implantation, the electrical characteristics of the end semiconductor device can be improved by decreasing the roughness of the silicon carbide semiconductor substrate surface. The semiconductor device of this invention is a Schottky barrier diode or a p-n type diode comprising at least one of a p type semiconductor region and n type semiconductor region selectively formed in a silicon carbide semiconductor region having an outermost surface layer surface that is a (000-1) surface or a surface inclined at an angle to the (000-1) surface, and a metal electrode formed on the outermost surface layer surface, that controls a direction in which electric current flows in a direction perpendicular to the outermost surface layer surface from application of a voltage to the metal electrode.Type: GrantFiled: November 25, 2003Date of Patent: May 26, 2009Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Kenji Fukuda, Ryoji Kosugi, Junji Senzaki, Shinsuke Harada
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Publication number: 20090057686Abstract: In a semiconductor device that uses a silicon carbide semiconductor substrate having p type, n type impurity semiconductor regions formed by ion implantation, the electrical characteristics of the end semiconductor device can be improved by decreasing the roughness of the silicon carbide semiconductor substrate surface. The semiconductor device of this invention is a Schottky barrier diode or a p-n type diode comprising at least one of a p type semiconductor region and n type semiconductor region selectively formed in a silicon carbide semiconductor region having an outermost surface layer surface that is a (000-1) surface or a surface inclined at an angle to the (000-1) surface, and a metal electrode formed on the outermost surface layer surface, that controls a direction in which electric current flows in a direction perpendicular to the outermost surface layer surface from application of a voltage to the metal electrode.Type: ApplicationFiled: October 30, 2008Publication date: March 5, 2009Applicant: National Institute of Adv. Industrial Sci. & Tech.Inventors: Kenji FUKUDA, Ryoji Kosugi, Junji Senzaki, Shinsuke Harada
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Patent number: 7256082Abstract: A method of manufacturing a semiconductor device that provides a semiconductor device having improved channel mobility includes a process of forming a gate insulation film of silicon oxide film, silicon nitride film or silicon oxide nitride film or the like on a silicon oxide substrate, and following formation of the gate insulation film on the silicon oxide substrate with heat treatment for a given time at a temperature range of 900° C. to 1000° C. in an atmosphere containing not less than 25% H2O (water).Type: GrantFiled: September 10, 2002Date of Patent: August 14, 2007Assignees: National Institute of Advanced Industrial Science and Technology, Sanyo Electric Co., Ltd.Inventors: Ryoji Kosugi, Kenji Fukuda, Junji Senzaki, Mitsuo Okamoto, Shinsuke Harada, Seiji Suzuki
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Publication number: 20060151806Abstract: In a semiconductor device that uses a silicon carbide semiconductor substrate having p type, n type impurity semiconductor regions formed by ion implantation, the electrical characteristics of the end semiconductor device can be improved by decreasing the roughness of the silicon carbide semiconductor substrate surface. The semiconductor device of this invention is a Schottky barrier diode or a p-n type diode comprising at least one of a p type semiconductor region and n type semiconductor region selectively formed in a silicon carbide semiconductor region having an outermost surface layer surface that is a (000-1) surface or a surface inclined at an angle to the (000-1) surface, and a metal electrode formed on the outermost surface layer surface, that controls a direction in which electric current flows in a direction perpendicular to the outermost surface layer surface from application of a voltage to the metal electrode.Type: ApplicationFiled: November 25, 2003Publication date: July 13, 2006Applicant: NATIONAL INSTITUTE OF ADV. INDUSTRIAL SCI. & TECHInventors: Kenji Fukuda, Ryoji Kosugi, Junji Senzaki, Shinsuke Harada
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Publication number: 20040242022Abstract: A method of manufacturing a semiconductor device that provides a semiconductor device having improved channel mobility includes a process of forming a gate insulation film of silicon oxide film, silicon nitride film or silicon oxide nitride film or the like on a silicon oxide substrate, and following formation of the gate insulation film on the silicon oxide substrate with heat treatment for a given time at a temperature range of 900° C. to 1000° C. in an atmosphere containing not less than 25% H2O (water).Type: ApplicationFiled: July 21, 2004Publication date: December 2, 2004Inventors: Ryoji Kosugi, Kenji Fukuda, Junji Senzaki, Mitsuo Okamoto, Shinsuke Harada, Seiji Suzuki
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Patent number: 6812102Abstract: In a semiconductor device using a silicon carbide substrate (1), the object of the present invention is to provide a method of manufacturing a semiconductor device that is a buried channel region type transistor having hot-carrier resistance, high punch-through resistance and high channel mobility. This is achieved by using a method of manufacturing a buried channel type transistor using a P-type silicon carbide substrate that includes a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500° C. or more after the step of forming the gate insulation layer. The gate insulation layer is formed by a thermal oxidation method using dry oxygen.Type: GrantFiled: December 30, 2003Date of Patent: November 2, 2004Assignees: National Institute of Advanced Industrial Science and Technology, Japan Science and Technology Corporation, Sanyo Electric Co., Ltd.Inventors: Kenji Fukuda, Kazuo Arai, Junji Senzaki, Shinsuke Harada, Ryoji Kosugi, Kazuhiro Adachi, Seiji Suzuki
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Patent number: 6764963Abstract: A semiconductor device is manufactured using a SiC substrate. On a semiconductor region a region formed of SiC having an (11-20) face orientation is formed. A gate insulation layer is a gate oxidation layer. The surface of the semiconductor region is cleaned, and the gate insulation layer is formed in an atmosphere containing hydrogen or water vapor. After the gate insulation layer has been formed, the substrate is heat-treated in an atmosphere containing hydrogen or water vapor. This reduces the interface-trap density at the interface between the gate oxidation layer and the semiconductor region.Type: GrantFiled: March 20, 2002Date of Patent: July 20, 2004Assignees: National Institute of Advanced Industrial Science and Technology, Sanyo Electric Co., Ltd.Inventors: Kenji Fukuda, Junji Senzaki, Ryoji Kosugi, Kazuo Arai, Seiji Suzuki
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Patent number: 6759684Abstract: An MIS transistor that uses a silicon carbide substrate has a buried channel structure. The surface orientation of the silicon carbide substrate is optimized so that the device does not assume a normally on state, has good hot-carrier endurance and punch-through endurance, and high channel mobility. In particular, a P-type silicon carbide semiconductor substrate is used to form a buried channel region. To achieve high mobility, the depth at which the buried channel region is formed is optimized, and the ratio between buried channel region junction depth (Lbc) source and drain region junction depth (Xj) is made to be within 0.2 to 1.0. The device can be formed on any surface of a hexagonal or rhombohedral or a (110) surface of a cubic system silicon carbide crystal, and provides a particularly good effect when formed on the (11-20) surface.Type: GrantFiled: November 14, 2001Date of Patent: July 6, 2004Assignees: National Institute of Advanced Industrial Science and Technology, Japan Science and Technology CorporationInventors: Kenji Fukuda, Kazuo Arai, Junji Senzaki, Shinsuke Harada, Ryoji Kosugi, Kazuhiro Adachi
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Publication number: 20040087093Abstract: In a semiconductor device using a silicon carbide substrate (1), the object of the present invention is to provide a method of manufacturing a semiconductor device that is a buried channel region type transistor having hot-carrier resistance, high punch-through resistance and high channel mobility. This is achieved by using a method of manufacturing a buried channel type transistor using a P-type silicon carbide substrate that includes a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500° C. or more after the step of forming the gate insulation layer. The gate insulation layer is formed by a thermal oxidation method using dry oxygen.Type: ApplicationFiled: December 30, 2003Publication date: May 6, 2004Inventors: Kenji Fukuda, Kazuo Arai, Junji Senzaki, Shinsuke Harada, Ryoji Kosugi, Kazuhiro Adachi, Seiji Suzuki
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Publication number: 20030013266Abstract: A semiconductor device is manufactured using a SiC substrate. On a semiconductor region a region formed of SiC having an (11-20) face orientation is formed. A gate insulation layer is a gate oxidation layer. The surface of the semiconductor region is cleaned, and the gate insulation layer is formed in an atmosphere containing hydrogen or water vapor After the gate insulation layer has been formed, the substrate is heat-treated in an atmosphere containing hydrogen or water vapor. This reduces the interface-trap and the semiconductor region.Type: ApplicationFiled: March 20, 2002Publication date: January 16, 2003Applicant: National Inst. of Advanced Ind. Science and Tech.Inventors: Kenji Fukuda, Junji Senzaki, Ryoji Kosugi, Kazuo Arai, Seiji Suzuki
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Publication number: 20020047125Abstract: An MIS transistor that uses a silicon carbide substrate has a buried channel structure. The surface orientation of the silicon carbide substrate is optimized so that the device does not assume a normally on state, has good hot-carrier endurance and punch-through endurance, and high channel mobility. In particular, a P-type silicon carbide semiconductor substrate is used to form a buried channel region. To achieve high mobility, the depth at which the buried channel region is formed is optimized, and the ratio between buried channel region junction depth (Lbc) source and drain region junction depth (Xj) is made to be within 0.2 to 1.0. The device can be formed on any surface of a hexagonal or rhombohedral or a (110) surface of a cubic system silicon carbide crystal, and provides a particularly good effect when formed on the (11-20) surface.Type: ApplicationFiled: November 14, 2001Publication date: April 25, 2002Applicant: Nat ' l Inst. of Advanced industrial and TechnologyInventors: Kenji Fukuda, Kazuo Arai, Junji Senzaki, Shinsuke Harada, Ryoji Kosugi, Kazuhiro Adachi