Patents by Inventor Ryoji Maruyama
Ryoji Maruyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140176051Abstract: A charging system can be connected to a power system and a storage battery unit, including: a charging apparatus that charges the storage battery unit; a measurement unit that measures at least one piece of information on a current, a voltage, and a harmonic wave of the power system; and a control apparatus that transmits to the charging apparatus, according to the at least one information measured by the measurement unit, a command for controlling charging with respect to the storage battery unit.Type: ApplicationFiled: January 14, 2014Publication date: June 26, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Hideki HAYASHI, Ryoji Maruyama, Yoshio Ebata
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Patent number: 6966783Abstract: A contact pin comprises a plunger contacting an electric part, a bottom contact portion electrically connected to a printed circuit board, and a spring urging the plunger and the bottom contact portion so as to separate from each other, in which at least one of the plunger and the bottom contact portion is formed by press-working a plate member. The bottom contact portion is provided with a connection portion to which the plunger is connected.Type: GrantFiled: July 9, 2003Date of Patent: November 22, 2005Assignee: Enplas CorporationInventors: Osamu Hachuda, Naoaki Takayama, Ryoji Maruyama
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Publication number: 20040029412Abstract: A contact pin comprises a plunger contacting an electric part, a bottom contact portion electrically connected to a printed circuit board, and a spring urging the plunger and the bottom contact portion so as to separate from each other, in which at least one of the plunger and the bottom contact portion is formed by press-working a plate member. The bottom contact portion is provided with a connection portion to which the plunger is connected.Type: ApplicationFiled: July 9, 2003Publication date: February 12, 2004Applicant: ENPLAS CORPORATIONInventors: Osamu Hachuda, Naoaki Takayama, Ryoji Maruyama
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Patent number: 6496783Abstract: A voltage (V1) and a current (A1), input from input terminals (T1) and (T2), are A/D converted to 1-bit output data by delta modulators and 1-bit output data of the delta modulator is delayed, using a phase-shifting circuit implemented by either a RAM (semiconductor memory) or shift registers, by an amount equivalent to 90° of the input voltage (V1), before a subsequent circuit performs a calculation of a reactive power. This circuit configuration reduces analog circuitry and enables a compact, low-cost implementation, even for use in an LSI.Type: GrantFiled: March 3, 2000Date of Patent: December 17, 2002Assignee: Kabushiki Kaisha ToshibaInventor: Ryoji Maruyama
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Patent number: 6473699Abstract: Power arithmetic apparatus detects a first variation amount of a voltage in proportion to a voltage of a measuring object and a second variation amount of a voltage in proportion to a current of the measuring object, and calculates power of the measuring object based on the first variation amount detected and the second variation amount detected.Type: GrantFiled: March 8, 1999Date of Patent: October 29, 2002Assignee: Kabushiki Kaisha ToshibaInventor: Ryoji Maruyama
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Publication number: 20020013668Abstract: According to the present invention, there is provided a power arithmetic apparatus comprising means for detecting a first variation amount of a voltage in proportion to a voltage of a measuring object and a second variation amount of a voltage in proportion to a current of the measuring object, and means for calculating power of the measuring object based on the first variation amount detected and the second variation amount detected.Type: ApplicationFiled: March 8, 1999Publication date: January 31, 2002Applicant: Kabushiki Kaisha ToshibaInventor: RYOJI MARUYAMA
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Patent number: 5924050Abstract: First and second 1-bit A/D converters convert respective input voltages being in direct proportion to voltage and current of a measurement system into respective 1 bit codes. First and second up-down counters whose up/down count in respective clock terminals are controlled in accordance with respective 1 bit codes which are output from the first and second 1-bit A/D converters, and output A/D converted values of the respective input voltages. A latch holds data one clock prior to currently input data and outputs the data. An adder-subtractor adds and subtracts respective output data of the first and second up-down counters and a numerical value 1 to and from output data of the latch under control of respective output data of the first and second 1-bit A/D converters and an exclusive OR value of the respective output data and outputs arithmetic data which being in proportion to a product of the respective input voltages to the latch. An adder integrates the output data of the latch.Type: GrantFiled: February 28, 1997Date of Patent: July 13, 1999Assignee: Kabushiki Kaisha ToshibaInventor: Ryoji Maruyama
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Patent number: 5554927Abstract: A device for measuring an electrical quantity of a system under measurement including a Hall element equipped with a pair of current input terminals and a pair of voltage output terminals. In the Hall element, four equivalent resistances are formed. The device also includes a device for applying a magnetic field proportional to a value of a first current on the Hall element, and a current supply circuit for flowing a second current between the current input terminals. The device further includes an output circuit for detecting a first voltage appearing between the output voltage terminals and outputting the first voltage as a measured value corresponding to the electrical quantity, and an offset compensation circuit for detecting an offset appearing between the voltage output terminals for varying one of the four equivalent resistances based on the offset thus detected so as to compensate the offset.Type: GrantFiled: March 3, 1995Date of Patent: September 10, 1996Assignee: Kabushiki Kaisha ToshibaInventor: Ryoji Maruyama
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Patent number: 5548151Abstract: In a Hall element, a semiconductor layer is surrounded by a first trench filled with an insulator. A first current supply portion of an n+-type semiconductor is disposed adjacent the semiconductor layer and the first trench. Second current supply portions are also disposed adjacent the semiconductor layer and the first trench and symmetrical with respect to the first current supply portion. Sensor portions of an n+-type semiconductor are disposed adjacent the semiconductor layer and the first trench at about the center between the first and second current supply portions, respectively. A magnetic flux perpendicular to the upper surface of the semiconductor layer can be detected by the foregoing arrangement.Type: GrantFiled: February 7, 1995Date of Patent: August 20, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Hideyuki Funaki, Hiroshi Mochizuki, Ryoji Maruyama, Kanae Fujii
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Patent number: 5438258Abstract: A power multiplication circuit including a Hall element for generating between voltage output terminals thereof a first output voltage corresponding to a power of a system under measurement. The circuit further includes a voltage polarity detection circuit for detecting a polarity of a power source voltage of the system and an operating circuit connected to receive the first output voltage and the polarity for amplifying the first output voltage and for changing over between amplified first output voltage and an inverted voltage of the amplified first output voltage to generate a second output voltage in accordance with the polarity. The circuit also includes an integrating amplifier circuit for integrating the second output voltage to generate an integrated signal and a variable resistance element connected between one of the voltage output terminals of the Hall element and ground, and connected to receive the integrated signal.Type: GrantFiled: July 30, 1993Date of Patent: August 1, 1995Assignee: Kabushiki Kaisha ToshibaInventor: Ryoji Maruyama
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Patent number: 5410594Abstract: A transmission input/output device for signal transmission through a telephone line, with reduced power consumption, size, and cost. The device includes: a resistor, connected to the telephone line, for setting a signal input and output impedance; and a transmission control circuit for amplifying the transmission signals to be outputted to the telephone line, including: a variable resistor, connected in series with the resistor, for supplying voltages corresponding to the transmission signals to be outputted to the telephone line into the resistor according to changes of an impedance of the variable resistor; and an operational amplifier for controlling the changes of the impedance of the variable resistor by supplying an output according to the transmission signals to be outputted to the variable resistor.Type: GrantFiled: February 28, 1991Date of Patent: April 25, 1995Assignee: Kabushiki Kaisha ToshibaInventor: Ryoji Maruyama
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Patent number: 4920312Abstract: A multiplier having pulse width modulators for modulating input signals into pulse signals whose pulse widths are corresponding to the levels of the input signals and which are asynchronous to each other; an oscillator for outputting a pulse signal at a frequency higher than any one of those of the pulse signals from the pulse width modulators; a logical gate portion which receives the pulse signals from the pulse width modulators as well as the pulse signal from the oscillator to executes predetermined logical operation on the pulse signals; and a subtracter which calculates, according to the pulse widths of the pulse signals from the pulse width modulators, the number of pulses outputted within a predetermined interval from the oscillator to provide a signal proportional to the product of levels of the input signals.Type: GrantFiled: September 22, 1988Date of Patent: April 24, 1990Assignee: Kabushiki Kaisha ToshibaInventor: Ryoji Maruyama
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Patent number: 4676589Abstract: An optical fiber coupler comprising a cylindrical fiber holder made of plastics, having a through bore of a size just capable of receiving an optical fiber to be connected and having a portion divided along the through bore in the middle range; a pair of flexible conical collars each of which is engaged with the end portion of the fiber holder and has a bore aligned with the through bore and a slit extending in the lengthwise direction; a cylindrical sleeve fitted on the cylindrical fiber holder to cover the fiber holder and having screw portions at both ends; and a pair of caps each of which is screwed with screw portion of the sleeve to grasp the optical fiber portion passing through the collar with the collar; and an opening aligned with the bore on its end wall, in order to enable to simplify the structure, to make small the entire size, to manufacture at a low cost and to assemble within a short time.Type: GrantFiled: January 11, 1985Date of Patent: June 30, 1987Assignee: Dai-Ichi Sekio Kabushiki KaishaInventors: Hidekazu Miyashita, Ryoji Maruyama