Patents by Inventor Ryoji Sakamoto

Ryoji Sakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6555850
    Abstract: A field-effect transistor has a composite channel structure having a first channel layer containing GaInP semiconductor and a second channel layer containing GaAs semiconductor. When the electric field is low in the channel, a channel current is primarily conducted in the second channel layer. When the electric field is high, the electrons flowing in the second channel layer move through real space transition to the first channel layer. These electrons conduct in the channel primarily in the first channel layer. Since GaInP semiconductor has a wider forbidden bandwidth than that of GaAs semiconductor, the avalanche breakdown voltage of GaInP semiconductor is higher than that of GaAs semiconductor. When the electric field is high, the conduction electrons travel in this GaInP semiconductor layer. This also improves the avalanche breakdown voltage of the field-effect transistor.
    Type: Grant
    Filed: February 17, 2000
    Date of Patent: April 29, 2003
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ryoji Sakamoto, Shigeru Nakajima
  • Patent number: 6333523
    Abstract: The present invention relates to a field-effect transistor which is improved such that the linearity of mutual conductance gm is flattened over a wider range of gate bias. This field-effect transistor is a MESFET comprising a channel layer and a cap layer in Schottky-contact with a gate electrode. In particular, between the channel layer and the cap layer, one or more auxiliary layers having a doping concentration lower than that of the channel layer and higher than that of the cap layer are provided. The doping concentration of one or more auxiliary layers is set such that the doping profile of a laminated structure constituted by the channel layer, one or more auxiliary layers, and cap layer exponentially lowers from the channel layer toward the cap layer. According to this configuration, the depletion layer can effectively be controlled over a wider range of gate bias, the long gate effect and the like are suppressed, and the linearity of mutual conductance gm is improved.
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: December 25, 2001
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ryoji Sakamoto, Tatsuya Hashinaga
  • Patent number: 5742480
    Abstract: It is an object of the present invention to provide a highly reliable optical module circuit board having a sufficient mechanical strength with respect to an external stress.
    Type: Grant
    Filed: November 2, 1995
    Date of Patent: April 21, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Sosaku Sawada, Ryoji Sakamoto, Hiromi Kurashima, Daisuke Takagi, Satoshi Ohe, Takeshi Sekiguchi, Nobuo Shiga
  • Patent number: 5596665
    Abstract: It is an object of the present invention to provide an optical module having a structure in which alignment precision of sleeves to be accommodated to a housing can be improved with a simple operation. The optical module according to the present invention is characterized by providing special structures for defining the positions of the sleeves to a sleeve holder for holding the sleeves, and the housing having a cavity for accommodating the sleeves. In particular, the housing includes support portions each having a reference surface for defining the fixing position of the corresponding sleeve. The sleeve holder includes spring pieces each for urging the sleeve to the reference surface.
    Type: Grant
    Filed: October 31, 1995
    Date of Patent: January 21, 1997
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiromi Kurashima, Hisato Takahashi, Ken-ichi Kitayama, Ryoji Sakamoto, Sosaku Sawada, Takeshi Sekiguchi, Ichiro Tonai, Nobuo Shiga