Abstract: Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.

Abstract: Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.

Abstract: Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.

Abstract: Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.

Abstract: Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.

Abstract: Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.

Abstract: First, a passivation film 3 having an opening K from which a part of the Al electrode 1 formed through an interlayer insulating film 2 made of a BPSG film is exposed is formed on a wafer. A wiring layer 7, which is connected to the Al electrode 1 exposed from the opening K and extended to the upper surface of the wafer, is formed. After a metal post 8 is formed on the wiring layer 7, a first groove TC1, which is located on the periphery of the chip inclusive of the wiring layer 7 and half cuts the wafer, is formed. The upper portion of the interlayer insulating film 2 is isotropically etched through the first groove TC1 to form a second groove TC2 having a larger opening diameter than that of the first groove TC1. The wafer surface inclusive of the wiring layer 7, second groove TC2 and first groove TC1 is resin-sealed to form an insulating resin layer R. Thereafter, a solder ball 12 is formed on the metal post 8 exposed from the insulating resin layer R.

Abstract: A metal post used with a chip size package and barrier metal formed on the metal post are omitted. After a second opening where a wiring layer is exposed is made, a second seed layer is formed and a solder post 7 is formed with the seed layer as a plate electrode.

Abstract: After a metal post 8 is formed on a semiconductor wafer 20, a groove 21 is formed in a first dicing step. The semiconductor wafer is resin-sealed by a rein layer R from its upper surface. The semiconductor wafer is ground from its lower surface to a depth reaching the bottom of the groove 21 so that the semiconductor wafer is divided into individual chips 20A. The resin layer is ground to expose the head of the metal post. After a solder ball is loaded on the metal post 8, the portion of the resin layer between adjacent chips 20A is diced in a second dicing step so that the individual chips 20A are separated from one another.

Abstract: A dielectric resin layer R covers a wiring layer 7 and a metal post 8 which are made of Cu. The dielectric resin layer is made of shrinkable resin whose film thickness is greatly reduced during thermal setting. This makes it unnecessary to perform a step of grinding the dielectric resin layer to expose a head of the metal post.

Abstract: To improve the moisture resistance of a chip size package, a seal ring 4 is made up of tungsten plugs and metal electrodes 11 and 12. Further, a spacer is formed on both or either of a first flank 13 and a second flank 14. The spacer can be formed on all interlayer insulating films extended to a dicing line part 3, whereby multiple seal rings can be provided.

Abstract: A process of exposing the head of a metal post used with a chip size package is simplified. A first semiconductor manufacturing method comprising the steps of forming an insulating resin layer R so as to completely cover the top of a metal post 8 and then polishing the resin layer so as to expose the head of the metal post, and a second semiconductor manufacturing method comprising the steps of forming an insulating resin layer R so as to completely cover the top of the metal post 8, then back grinding the wafer rear face, and then polishing the resin layer R so as to expose the head of the metal post are provided.

Abstract: A removal area EL is provided as a first dicing line in a dicing area, coat materials 6′ and 7′ are put on the flanks of the removal area, a resin layer R is formed, and a dicing blade narrower than the width of the removal area EL is used to fully cut on a second dicing line, whereby the interface exposed by the first dicing can be coated and protected.