Patents by Inventor Ryoko Miyanaga
Ryoko Miyanaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8759190Abstract: A current steering element (100) formed such that the current steering element covers a lower opening (105) of a via hole (104) formed in an interlayer insulating layer (102), comprises: a corrosion-suppressing layer (106) formed on a lower side of a lower opening of the via hole such that the corrosion-suppressing layer covers an entire portion of the lower opening; a second electrode layer (108) formed under the corrosion-suppressing layer and comprising a material different from a material of the corrosion-suppressing layer; a current steering layer (110) formed under the second electrode layer such that the current steering layer is physically in contact with the second electrode layer; and a first electrode layer (112) formed under the current steering layer such that the first electrode layer is physically in contact with the current steering layer; and the first electrode layer, the current steering layer and the second electrode layer constitute one of a MSM diode and a MIM diode.Type: GrantFiled: September 16, 2011Date of Patent: June 24, 2014Assignee: Panasonic CorporationInventors: Ryoko Miyanaga, Takumi Mikawa, Yukio Hayakawa, Takeki Ninomiya, Koji Arita
-
Publication number: 20130171799Abstract: A current steering element (100) formed such that the current steering element covers a lower opening (105) of a via hole (104) formed in an interlayer insulating layer (102), comprises: a corrosion-suppressing layer (106) formed on a lower side of a lower opening of the via hole such that the corrosion-suppressing layer covers an entire portion of the lower opening; a second electrode layer (108) formed under the corrosion-suppressing layer and comprising a material different from a material of the corrosion-suppressing layer; a current steering layer (110) formed under the second electrode layer such that the current steering layer is physically in contact with the second electrode layer; and a first electrode layer (112) formed under the current steering layer such that the first electrode layer is physically in contact with the current steering layer; and the first electrode layer, the current steering layer and the second electrode layer constitute one of a MSM diode and a MIM diode.Type: ApplicationFiled: September 16, 2011Publication date: July 4, 2013Applicant: PANASONIC CORPORATIONInventors: Ryoko Miyanaga, Takumi Mikawa, Yukio Hayakawa, Takeki Ninomiya, Koji Arita
-
Patent number: 8445319Abstract: A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0<x<2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x<y<2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer.Type: GrantFiled: August 8, 2011Date of Patent: May 21, 2013Assignee: Panasonic CorporationInventors: Yoshihiko Kanzawa, Koji Katayama, Satoru Fujii, Shunsaku Muraoka, Koichi Osano, Satoru Mitani, Ryoko Miyanaga, Takeshi Takagi, Kazuhiko Shimakawa
-
Patent number: 8389990Abstract: A nonvolatile semiconductor memory device of the present invention includes a substrate (1), first wires (2), memory cells each including a resistance variable element (5) and a portion of a diode element (6), second wires (11) which respectively cross the first wires (2) to be perpendicular to the first wires (2) and each of which contains a remaining portion of the diode element (6), and upper wires (13) formed via an interlayer insulating layer (12), respectively, and the first wires (2) are connected to the upper wires (13) via first contacts (14), respectively, and the second wires (11) are connected to the upper wires (13) via second contacts (15), respectively.Type: GrantFiled: May 31, 2012Date of Patent: March 5, 2013Assignee: Panasonic CorporationInventors: Takumi Mikawa, Yoshio Kawashima, Ryoko Miyanaga
-
Patent number: 8344345Abstract: A first wire layer (19) including first memory wires (12) is connected to a second wire layer (20) including second memory wires (17) via first contacts (21) penetrating a first interlayer insulating layer (13). The first wire layer (13) is connected to and led out to upper wires (22) via second contacts (26) connected to the second wire layer (20) and penetrating the second interlayer insulating layer (18). The first contacts (21) penetrate semiconductor layer (17b) or insulator layer (17c) of the second wire layer (20).Type: GrantFiled: December 26, 2008Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventors: Takumi Mikawa, Yoshio Kawashima, Ryoko Miyanaga
-
Publication number: 20120298945Abstract: A nonvolatile semiconductor memory device of the present invention includes a substrate (1), first wires (2), memory cells each including a resistance variable element (5) and a portion of a diode element (6), second wires (11) which respectively cross the first wires (2) to be perpendicular to the first wires (2) and each of which contains a remaining portion of the diode element (6), and upper wires (13) formed via an interlayer insulating layer (12), respectively, and the first wires (2) are connected to the upper wires (13) via first contacts (14), respectively, and the second wires (11) are connected to the upper wires (13) via second contacts (15), respectively.Type: ApplicationFiled: May 31, 2012Publication date: November 29, 2012Applicant: Panasonic CorporationInventors: Takumi MIKAWA, Yoshio Kawashima, Ryoko Miyanaga
-
Patent number: 8309946Abstract: A resistance variable element of the present invention comprises a first electrode (103), a second electrode (107), and a resistance variable layer which is interposed between the first electrode (103) and the second electrode (107) to contact the first electrode (103) and the second electrode (107), the resistance variable layer being configured to change in response to electric signals with different polarities which are applied between the first electrode (103) and the second electrode (107), the resistance variable layer comprising an oxygen-deficient transition metal oxide layer, and the second electrode (107) comprising platinum having minute hillocks (108).Type: GrantFiled: July 22, 2009Date of Patent: November 13, 2012Assignee: Panasonic CorporationInventors: Satoru Mitani, Shunsaku Muraoka, Yoshihiko Kanzawa, Koji Katayama, Ryoko Miyanaga, Satoru Fujii, Takeshi Takagi
-
Patent number: 8253136Abstract: A nonvolatile semiconductor memory device of the present invention includes a substrate (1), first wires (2), memory cells each including a resistance variable element (5) and a portion of a diode element (6), second wires (11) which respectively cross the first wires (2) to be perpendicular to the first wires (2) and each of which contains a remaining portion of the diode element (6), and upper wires (13) formed via an interlayer insulating layer (12), respectively, and the first wires (2) are connected to the upper wires (13) via first contacts (14), respectively, and the second wires (11) are connected to the upper wires (13) via second contacts (15), respectively.Type: GrantFiled: October 22, 2008Date of Patent: August 28, 2012Assignee: Panasonic CorporationInventors: Takumi Mikawa, Yoshio Kawashima, Ryoko Miyanaga
-
Patent number: 8242479Abstract: A nonvolatile memory device includes via holes (12) formed at cross sections where first wires (11) cross second wires (14), respectively, and current control elements (13) each including a current control layer (13b), a first electrode layer (13a) and a second electrode layer (13c) such that the current control layer (13b) is sandwiched between the first electrode layer (13a) and the second electrode layer (13c), in which resistance variable elements (15) are provided inside the via holes (12), respectively, the first electrode layer (13a) is disposed so as to cover the via hole (12), the current control layer (13b) is disposed so as to cover the first electrode layer (13a), the second electrode layer (13c) is disposed on the current control layer (13b), a wire layer (14a) of the second wire is disposed on the second electrode layer (13c), and the second wires (14) each includes the current control layer (13b), the second electrode layer (13c) and the wire layer (14a) of the second wire.Type: GrantFiled: November 14, 2008Date of Patent: August 14, 2012Assignee: Panasonic CorporationInventors: Yoshio Kawashima, Takumi Mikawa, Ryoko Miyanaga, Takeshi Takagi
-
Publication number: 20110294259Abstract: A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0<x<2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x<y<2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer.Type: ApplicationFiled: August 8, 2011Publication date: December 1, 2011Applicant: Panasonic CorporationInventors: Yoshihiko KANZAWA, Koji Katayama, Satoru Fujii, Shunsaku Muraoka, Koichi Osano, Satoru Mitani, Ryoko Miyanaga, Takeshi Takagi, Kazuhiko Shimakawa
-
Patent number: 8022502Abstract: A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0<x<2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x<y<2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer.Type: GrantFiled: March 26, 2008Date of Patent: September 20, 2011Assignee: Panasonic CorporationInventors: Yoshihiko Kanzawa, Koji Katayama, Satoru Fujii, Shunsaku Muraoka, Koichi Osano, Satoru Mitani, Ryoko Miyanaga, Takeshi Takagi, Kazuhiko Shimakawa
-
Publication number: 20110031465Abstract: A resistance variable element of the present invention comprises a first electrode (103), a second electrode (107), and a resistance variable layer which is interposed between the first electrode (103) and the second electrode (107) to contact the first electrode (103) and the second electrode (107), the resistance variable layer being configured to change in response to electric signals with different polarities which are applied between the first electrode (103) and the second electrode (107), the resistance variable layer comprising an oxygen-deficient transition metal oxide layer, and the second electrode (107) comprising platinum having minute hillocks (108).Type: ApplicationFiled: July 22, 2009Publication date: February 10, 2011Applicant: PANASONIC CORPORATIONInventors: Satoru Mitani, Shunsaku Muraoka, Yoshihiko Kanzawa, Koji Katayama, Ryoko Miyanaga, Satoru Fujii, Takeshi Takaji
-
Publication number: 20100283026Abstract: A first wire layer (19) including first memory wires (12) is connected to a second wire layer (20) including second memory wires (17) via first contacts (21) penetrating a first interlayer insulating layer (13). The first wire layer (13) is connected to and led out to upper wires (22) via second contacts (26) connected to the second wire layer (20) and penetrating the second interlayer insulating layer (18). The first contacts (21) penetrate semiconductor layer (17b) or insulator layer (17c) of the second wire layer (20).Type: ApplicationFiled: December 26, 2008Publication date: November 11, 2010Inventors: Takumi Mikawa, Yoshio Kawashima, Ryoko Miyanaga
-
Publication number: 20100264392Abstract: A nonvolatile memory device includes via holes (12) formed at cross sections where first wires (11) cross second wires (14), respectively, and current control elements (13) each including a current control layer (13b), a first electrode layer (13a) and a second electrode layer (13c) such that the current control layer (13b) is sandwiched between the first electrode layer (13a) and the second electrode layer (13c), in which resistance variable elements (15) are provided inside the via holes (12), respectively, the first electrode layer (13a) is disposed so as to cover the via hole (12), the current control layer (13b) is disposed so as to cover the first electrode layer (13a), the second electrode layer (13c) is disposed on the current control layer (13b), a wire layer (14a) of the second wire is disposed on the second electrode layer (13c), and the second wires (14) each includes the current control layer (13b), the second electrode layer (13c) and the wire layer (14a) of the second wire.Type: ApplicationFiled: November 14, 2008Publication date: October 21, 2010Inventors: Yoshio Kawashima, Takumi Mikawa, Ryoko Miyanaga, Takeshi Takagi
-
Patent number: 7816688Abstract: An upper part of a SIC substrate 1 is oxidized at a temperature of 800 to 1400° C., inclusive, in an oxygen atmosphere at 1.4×102 Pa or less, thereby forming a first insulating film 2 which is a thermal oxide film of 20 nm or less in thickness. Thereafter, annealing is performed, and then a first cap layer 3, which is a nitride film of about 5 nm in thickness, is formed thereon by CVD. A second insulating film 4, which is an oxide film of about 130 nm in thickness, is deposited thereon by CVD. A second cap layer 5, which is a nitride film of about 10 nm in thickness, is formed thereon. In this manner, a gate insulating film 6 made of the first insulating film 2 through the second cap layer 5 is formed, thus obtaining a low-loss highly-reliable semiconductor device.Type: GrantFiled: November 27, 2002Date of Patent: October 19, 2010Assignee: Panasonic CorporationInventors: Kenya Yamashita, Makoto Kitabatake, Kunimasa Takahashi, Osamu Kusumoto, Masao Uchida, Ryoko Miyanaga
-
Publication number: 20100237313Abstract: A nonvolatile semiconductor memory device of the present invention includes a substrate (1), first wires (2), memory cells each including a resistance variable element (5) and a portion of a diode element (6), second wires (11) which respectively cross the first wires (2) to be perpendicular to the first wires (2) and each of which contains a remaining portion of the diode element (6), and upper wires (13) formed via an interlayer insulating layer (12), respectively, and the first wires (2) are connected to the upper wires (13) via first contacts (14), respectively, and the second wires (11) are connected to the upper wires (13) via second contacts (15), respectively.Type: ApplicationFiled: October 22, 2008Publication date: September 23, 2010Inventors: Takumi Mikawa, Yoshio Kawashima, Ryoko Miyanaga
-
Patent number: 7709403Abstract: A gate insulating film which is an oxide layer mainly made of SiO2 is formed over a silicon carbide substrate by thermal oxidation, and then, a resultant structure is annealed in an inert gas atmosphere in a chamber. Thereafter, the silicon carbide-oxide layered structure is placed in a chamber which has a vacuum pump and exposed to a reduced pressure NO gas atmosphere at a high temperature higher than 1100° C. and lower than 1250° C., whereby nitrogen is diffused in the gate insulating film. As a result, a gate insulating film which is a V-group element containing oxide layer, the lower part of which includes a high nitrogen concentration region, and the relative dielectric constant of which is 3.0 or higher, is obtained. The interface state density of an interface region between the V-group element containing oxide layer and the silicon carbide layer decreases.Type: GrantFiled: October 4, 2004Date of Patent: May 4, 2010Assignee: Panasonic CorporationInventors: Kenya Yamashita, Makoto Kitabatake, Osamu Kusumoto, Kunimasa Takahashi, Masao Uchida, Ryoko Miyanaga
-
Publication number: 20090283736Abstract: A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0<x<2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x<y<2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer.Type: ApplicationFiled: March 26, 2008Publication date: November 19, 2009Inventors: Yoshihiko Kanzawa, Koji Katayama, Satoru Fujii, Shunsaku Muraoka, Koichi Osano, Satoru Mitani, Ryoko Miyanaga, Takeshi Takagi, Kazuhlko Shimakawa
-
Patent number: 7507999Abstract: An accumulation-mode MISFET comprises: a high-resistance SiC layer 102 epitaxially grown on a SiC substrate 101; a well region 103; an accumulation channel layer 104 having a multiple ?-doped layer formed on the surface region of the well region 103; a contact region 105; a gate insulating film 108; and a gate electrode 110. The accumulation channel layer 104 has a structure in which undoped layers 104b and ?-doped layers 104a allowing spreading movement of carriers to the undoped layers 104b under a quantum effect are alternately stacked. A source electrode 111 is provided which enters into the accumulation channel layer 104 and the contact region 105 to come into direct contact with the contact region 105. It becomes unnecessary that a source region is formed by ion implantation, leading to reduction in fabrication cost.Type: GrantFiled: July 9, 2003Date of Patent: March 24, 2009Assignee: Panasonic CorporationInventors: Osamu Kusumoto, Makoto Kitabatake, Kunimasa Takahashi, Kenya Yamashita, Ryoko Miyanaga, Masao Uchida
-
Patent number: 7462540Abstract: A method for fabricating a semiconductor device includes the steps of implanting ions into a silicon carbide thin film (2) formed on a silicon carbide substrate (1), heating the silicon carbide substrate in a reduced pressure atmosphere to form a carbon layer (5) on the surface of the silicon carbide substrate, and performing activation annealing with respect to the silicon carbide substrate in an atmosphere under a pressure higher than in the step of forming the carbon layer (5) and at a temperature higher than in the step of forming the carbon layer (5).Type: GrantFiled: January 28, 2005Date of Patent: December 9, 2008Assignee: Panasonic CorporationInventors: Kunimasa Takahashi, Makoto Kitabatake, Kenya Yamashita, Masao Uchida, Osamu Kusumoto, Ryoko Miyanaga