Patents by Inventor Ryosuke KATAOKA

Ryosuke KATAOKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240110970
    Abstract: Main cells that constitute a semiconductor element having a trench gate structure include first cells, and second cells having a structure in which gate insulating films are more easily broken by energization than those in the first cells, and the number of which is smaller than that of the first cells. At a time of driving the semiconductor element, a common gate drive voltage is applied to gate electrodes of the first cells and the second cells. An electrical characteristic is measured to detect failure of the second cells due to energization at the time of driving. The gate electrodes of the failed second cells are electrically isolated from the gate electrodes of the first cells so that the gate drive voltage is not applied to the failed second cells. The failure of the first cells is predicted based on the failure of the second cells.
    Type: Application
    Filed: December 13, 2023
    Publication date: April 4, 2024
    Applicant: DENSO CORPORATION
    Inventors: Masataka DEGUCHI, Junya MURAMATSU, Keita KATAOKA, Katsuhiro KUTSUKI, Isao AOYAGI, Takashi TOMINAGA, Ryosuke OKACHI, Takashi KOHYAMA
  • Patent number: 11075071
    Abstract: To provide a wafer processing method which can simplify the wafer processing process and efficiently obtain chips of stable quality. A wafer processing method includes: a tape attaching step of attaching a back grinding tape to the front surface of a wafer; a modified region forming step of applying a laser beam from the back surface of the wafer along a cut line to form modified regions inside the wafer; a back surface processing step of processing the back surface of the wafer having the modified regions to reduce a thickness of the wafer; and a dividing step of, in a state in which the back grinding tape is attached to the front surface of the wafer, applying a load to the cut line from the back surface of the wafer to divide the wafer along the cut line and obtain individual chips.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: July 27, 2021
    Assignee: TOKYO SEIMITSU CO., LTD.
    Inventors: Ryosuke Kataoka, Takashi Tamogami, Syuhei Oshida
  • Publication number: 20200266047
    Abstract: To provide a wafer processing method which can simplify the wafer processing process and efficiently obtain chips of stable quality. A wafer processing method includes: a tape attaching step of attaching a back grinding tape to the front surface of a wafer; a modified region forming step of applying a laser beam from the back surface of the wafer along a cut line to form modified regions inside the wafer; a back surface processing step of processing the back surface of the wafer having the modified regions to reduce a thickness of the wafer; and a dividing step of, in a state in which the back grinding tape is attached to the front surface of the wafer, applying a load to the cut line from the back surface of the wafer to divide the wafer along the cut line and obtain individual chips.
    Type: Application
    Filed: May 5, 2020
    Publication date: August 20, 2020
    Applicant: Tokyo Seimitsu Co., Ltd.
    Inventors: Ryosuke KATAOKA, Takashi TAMOGAMI, Syuhei OSHIDA