Abstract: An information processing apparatus includes a processing unit configured to issue a read command to a device, a memory configured to store data, and a switching controller configured to connect the processing unit, the memory, and the device. The switching controller includes a command detection circuit configured to detect the read command issued from the processing unit, a command processing circuit configured to process the read command and to output the processed read command, and a pre-read request issuance circuit configured to generate a read request for at least part of data within data specified by the read command and to transmit the read request to the memory. The switching controller receives the part of the data from the memory, and transmits the part of the data to the device.

Abstract: A processor core adopts a pipeline processing method and has an interlock mechanism. A built-in accelerator executes a specific processing in place of the processor core. When a processing is executed by the built-in accelerator and there is no processing to be executed by the processor core, the interlock mechanism stops and restarts the pipeline processing in response to a start of processing and a processing completion of the built-in accelerator, respectively. A processing-completion waiting operation to the built-in accelerator is implemented by using the interlock mechanism, and thus useless power consumption of the processor core during the processing of the built-in accelerator can be easily reduced.

Abstract: A processor core adopts a pipeline processing method and has an interlock mechanism. A built-in accelerator executes a specific processing in place of the processor core. When a processing is executed by the built-in accelerator and there is no processing to be executed by the processor core, the interlock mechanism stops and restarts the pipeline processing in response to a start of processing and a processing completion of the built-in accelerator, respectively. A processing-completion waiting operation to the built-in accelerator is implemented by using the interlock mechanism, and thus useless power consumption of the processor core during the processing of the built-in accelerator can be easily reduced.