Patents by Inventor Ryosuke Kubota

Ryosuke Kubota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210111541
    Abstract: A light-emitting module includes a substrate, a first surface-emitting laser mounted on the substrate, the first surface-emitting laser having a first engaging portion protruded outward at an end, and a second surface-emitting laser mounted on the substrate, the second surface-emitting laser having a second engaging portion recessed inward at an end. The first surface-emitting laser and the second surface-emitting laser are adjacent to each other. The first engaging portion and the second engaging portion are engaged with each other.
    Type: Application
    Filed: September 17, 2020
    Publication date: April 15, 2021
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Ryosuke KUBOTA
  • Patent number: 10429345
    Abstract: Electrophoresis device including: a first flow passage extending in a first direction and through which a sample and a buffer solution flow; a sample collecting part provided at an end portion of the first flow passage and configured to collect the sample; electrodes disposed at both sides of the first flow passage in a second direction perpendicular to the first direction and configured to apply a voltage to the first flow passage in the second direction; second flow passages communicating with both sides of the first flow passage in the second direction, configured to accommodate the electrodes, and through which a second buffer solution flows; and partition walls fixed to communicating portions between the first and second flow passages with a predetermined bonding strength and configured to block movement of substances between the first and second flow passages. The partition walls are formed of a gel material having ion permeability.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: October 1, 2019
    Assignee: THE UNIVERSITY OF TOKYO
    Inventors: Takanori Ichiki, Takanori Akagi, Ryosuke Kubota
  • Patent number: 10416227
    Abstract: A method of fabricating a surface-emitting laser includes the steps of fabricating a substrate product including device sections, a pad electrode, and a conductor, each of the device sections including a surface-emitting laser having an electrode, the conductor connecting the pad electrode to the electrode across a boundary of the device sections; attaching a connection device to the substrate product, the connection device including a probe device having a probe and a probe support base having an opening; performing a burn-in test of the surface-emitting lasers by applying electric power to the pad electrode through the probe at a high temperature; and after the burn-in test, separating the substrate product into semiconductor chips. The burn-in test includes a step of monitoring light emitted by the surface-emitting laser through the opening during the burn-in test, and a step of selecting the surface-emitting lasers based on a monitoring result.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: September 17, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Ryosuke Kubota
  • Patent number: 10340344
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, and a gate electrode. The gate insulating film is provided as being in contact with the first main surface of the silicon carbide substrate. The gate electrode is provided on the gate insulating film such that the gate insulating film lies between the gate electrode and the silicon carbide substrate. In a first stress test in which a gate voltage of ?5 V is applied to the gate electrode for 100 hours at a temperature of 175° C., an absolute value of a difference between a first threshold voltage and a second threshold voltage is not more than 0.5 V, with a threshold voltage before the first stress test being defined as the first threshold voltage and a threshold voltage after the first stress test being defined as the second threshold voltage.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: July 2, 2019
    Assignees: Sumitomo Electric Industries, Ltd., Renesas Electronics Corporation
    Inventors: Ryosuke Kubota, Shunsuke Yamada, Taku Horii, Takeyoshi Masuda, Daisuke Hamajima, So Tanaka, Shinji Kimura, Masayuki Kobayashi
  • Publication number: 20190052059
    Abstract: A surface-emitting laser includes a substrate having a principal surface; an active layer provided on the principal surface of the substrate; a first stacked layer provided on the active layer, the first stacked layer serving as a first distributed Bragg reflector; a first contact layer disposed between the active layer and the first stacked layer; a post provided on the principal surface of the substrate, the post including the active layer, the first contact layer, and the first stacked layer, the post having an upper surface, a side surface inclined relative to the substrate principle surface, and a lower end; and a first electrode that contacts the first contact layer at the side surface of the post.
    Type: Application
    Filed: April 4, 2018
    Publication date: February 14, 2019
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Ryosuke Kubota
  • Publication number: 20180356459
    Abstract: A method of fabricating a surface-emitting laser includes the steps of fabricating a substrate product including device sections, a pad electrode, and a conductor, each of the device sections including a surface-emitting laser having an electrode, the conductor connecting the pad electrode to the electrode across a boundary of the device sections; attaching a connection device to the substrate product, the connection device including a probe device having a probe and a probe support base having an opening; performing a burn-in test of the surface-emitting lasers by applying electric power to the pad electrode through the probe at a high temperature; and after the burn-in test, separating the substrate product into semiconductor chips. The burn-in test includes a step of monitoring light emitted by the surface-emitting laser through the opening during the burn-in test, and a step of selecting the surface-emitting lasers based on a monitoring result.
    Type: Application
    Filed: March 23, 2018
    Publication date: December 13, 2018
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Ryosuke KUBOTA
  • Patent number: 10050109
    Abstract: A silicon carbide semiconductor substrate includes: a base substrate that has a main surface having an outer diameter of not less than 100 mm and that is made of single-crystal silicon carbide; and an epitaxial layer formed on the main surface. The silicon carbide semiconductor substrate has an amount of warpage of not less than ?100 ?m and not more than 100 ?m when a substrate temperature is a room temperature and has an amount of warpage of not less than ?1.5 mm and not more than 1.5 mm when the substrate temperature is 400° C.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: August 14, 2018
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Ryosuke Kubota, Takeyoshi Masuda
  • Publication number: 20180138275
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, and a gate electrode. The gate insulating film is provided as being in contact with the first main surface of the silicon carbide substrate. The gate electrode is provided on the gate insulating film such that the gate insulating film lies between the gate electrode and the silicon carbide substrate. In a first stress test in which a gate voltage of ?5 V is applied to the gate electrode for 100 hours at a temperature of 175° C., an absolute value of a difference between a first threshold voltage and a second threshold voltage is not more than 0.5 V, with a threshold voltage before the first stress test being defined as the first threshold voltage and a threshold voltage after the first stress test being defined as the second threshold voltage.
    Type: Application
    Filed: January 12, 2018
    Publication date: May 17, 2018
    Inventors: Ryosuke Kubota, Shunsuke Yamada, Taku Horii, Takeyoshi Masuda, Daisuke Hamajima, So Tanaka, Shinji Kimura, Masayuki Kobayashi
  • Patent number: 9966249
    Abstract: A silicon carbide semiconductor substrate includes a first main surface and a second main surface opposite to the first main surface. The first main surface has a maximum diameter of more than 100 mm, and the silicon carbide semiconductor substrate has a thickness of not more than 700 ?m. A dislocation density is not more than 500/mm2 at an arbitrary region having an area of 1 mm2 in a region within 5 mm from an outer circumferential end portion of the first main surface toward a center of the first main surface. Accordingly, there is provided a silicon carbide semiconductor substrate allowing for suppression of generation of cracks.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: May 8, 2018
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: So Tanaka, Kyoko Okita, Taro Nishiguchi, Ryosuke Kubota, Kenji Kanbara
  • Patent number: 9905653
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, and a gate electrode. The gate insulating film is provided as being in contact with the first main surface of the silicon carbide substrate. The gate electrode is provided on the gate insulating film such that the gate insulating film lies between the gate electrode and the silicon carbide substrate. In a first stress test in which a gate voltage of ?5 V is applied to the gate electrode for 100 hours at a temperature of 175° C., an absolute value of a difference between a first threshold voltage and a second threshold voltage is not more than 0.5 V, with a threshold voltage before the first stress test being defined as the first threshold voltage and a threshold voltage after the first stress test being defined as the second threshold voltage.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: February 27, 2018
    Assignees: Sumitomo Electric Industries, Ltd., Renesas Electronics Corporation
    Inventors: Ryosuke Kubota, Shunsuke Yamada, Taku Horii, Takeyoshi Masuda, Daisuke Hamajima, So Tanaka, Shinji Kimura, Masayuki Kobayashi
  • Patent number: 9887101
    Abstract: A method for manufacturing a semiconductor device in accordance with the present invention includes the steps of preparing a semiconductor substrate, placing the semiconductor substrate on an electrostatic chuck, chucking the semiconductor substrate after raising a temperature of the electrostatic chuck to a first temperature, raising a temperature of the electrostatic chuck to a second temperature which is higher than the above-described first temperature in a state where the semiconductor substrate is chucked, and performing a treatment to the semiconductor substrate in a state where a temperature of the electrostatic chuck is maintained at the above-described second temperature.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: February 6, 2018
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ryosuke Kubota, So Tanaka
  • Patent number: 9831080
    Abstract: A method for manufacturing a semiconductor device includes a step of preparing a SiC substrate, a step of fixing the SiC substrate on an electrostatic chuck and heat-treating the SiC substrate, and a step of performing ion implantation treatment on the SiC substrate fixed on the electrostatic chuck and heat-treated. The step of heat-treating includes an outer circumferential-side chucking step which generates an electrostatic attraction force between an outer circumferential region of the SiC substrate and an outer circumferential portion of the electrostatic chuck, the outer circumferential portion facing the outer circumferential region, and an inner circumferential-side chucking step which is started after the outer circumferential-side chucking step is started, and generates an electrostatic attraction force between an inner circumferential region of the SiC substrate and an inner circumferential portion of the electrostatic chuck, the inner circumferential portion facing the inner circumferential region.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: November 28, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ryosuke Kubota, Ren Kimura, So Tanaka, Kazuhito Kobashi
  • Patent number: 9806167
    Abstract: The steps of preparing a silicon carbide layer having a main surface, forming on the main surface, a first mask layer located on a first region to be a channel region and having a first opening portion on each of opposing regions with the first region lying therebetween, and forming a high-concentration impurity region having a first conductivity type and being higher in impurity concentration than the silicon carbide layer in a region exposed through the first opening portion, by implanting ions into the main surface with the first mask layer being interposed are included.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: October 31, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Takeyoshi Masuda, Ryosuke Kubota
  • Patent number: 9786741
    Abstract: A silicon carbide semiconductor device includes a silicon carbide layer and a gate insulating layer. The silicon carbide layer has a main surface. The gate insulating layer is arranged as being in contact with the main surface of the silicon carbide layer. The silicon carbide layer includes a drift region having a first conductivity type, a body region having a second conductivity type different from the first conductivity type and being in contact with the drift region, a source region having the first conductivity type and arranged as being spaced apart from the drift region by the body region, and a protruding region arranged to protrude from at least one side of the source region and the drift region into the body region, being in contact with the gate insulating layer, and having the first conductivity type.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: October 10, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Taku Horii, Ryosuke Kubota
  • Publication number: 20170248878
    Abstract: According to an aspect of the invention, an elastic roll includes a base that has a circular outer circumferential line in an axial direction and includes an outer circumferential surface on which a spiral recess in the axial direction is formed; and an elastic layer that is provided to be adhered to the outer circumferential surface and has a circular outer circumferential line in the axial direction.
    Type: Application
    Filed: August 10, 2016
    Publication date: August 31, 2017
    Applicant: FUJI XEROX CO., LTD.
    Inventor: Ryosuke KUBOTA
  • Publication number: 20170234832
    Abstract: Electrophoresis device including: a first flow passage extending in a first direction and through which a sample and a buffer solution flow; a sample collecting part provided at an end portion of the first flow passage and configured to collect the sample; electrodes disposed at both sides of the first flow passage in a second direction perpendicular to the first direction and configured to apply a voltage to the first flow passage in the second direction; second flow passages communicating with both sides of the first flow passage in the second direction, configured to accommodate the electrodes, and through which a second buffer solution flows; and partition walls fixed to communicating portions between the first and second flow passages with a predetermined bonding strength and configured to block movement of substances between the first and second flow passages. The partition walls are formed of a gel material having ion permeability.
    Type: Application
    Filed: August 28, 2015
    Publication date: August 17, 2017
    Applicant: The University of Tokyo
    Inventors: Takanori Ichiki, Takanori Akagi, Ryosuke Kubota
  • Patent number: 9691608
    Abstract: A method for manufacturing a silicon carbide substrate includes the following steps. There is prepared a silicon carbide single crystal substrate having a first main surface, a second main surface, and a first side end portion, the second main surface being opposite to the first main surface, the first side end portion connecting the first main surface and the second main surface to each other, the first main surface having a width with a maximum value of more than 100 mm. A silicon carbide epitaxial layer is formed in contact with the first side end portion, the first main surface, and a boundary between the first main surface and the first side end portion. The silicon carbide epitaxial layer formed in contact with the first side end portion and the boundary is removed.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: June 27, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: So Tanaka, Shunsuke Yamada, Taku Horii, Akira Matsushima, Ryosuke Kubota, Kyoko Okita, Takayuki Nishiura
  • Publication number: 20170154953
    Abstract: A silicon carbide semiconductor device includes an impurity region including a p type impurity and disposed within a silicon carbide layer to surround an element region as seen in plan view. The impurity region has a peak concentration of the p type impurity at a position within the silicon carbide layer distant from a first main surface. The peak concentration is not less than 1×1016 cm?3 and not more than 5×1017 cm?3. The impurity region is formed by implanting ions of the p type impurity into the silicon carbide layer. Then, a silicon dioxide film is formed to cover the first main surface of the silicon carbide layer by performing a thermal oxidation process on the silicon carbide layer, and the concentration of the p type impurity in the vicinity of the first main surface is lowered.
    Type: Application
    Filed: May 8, 2015
    Publication date: June 1, 2017
    Inventors: Keiji Wada, Ryosuke Kubota, Toru Hiyoshi
  • Publication number: 20170076934
    Abstract: A method for manufacturing a semiconductor device includes a step of preparing a SiC substrate, a step of fixing the SiC substrate on an electrostatic chuck and heat-treating the SiC substrate, and a step of performing ion implantation treatment on the SiC substrate fixed on the electrostatic chuck and heat-treated. The step of heat-treating includes an outer circumferential-side chucking step which generates an electrostatic attraction force between an outer circumferential region of the SiC substrate and an outer circumferential portion of the electrostatic chuck, the outer circumferential portion facing the outer circumferential region, and an inner circumferential-side chucking step which is started after the outer circumferential-side chucking step is started, and generates an electrostatic attraction force between an inner circumferential region of the SiC substrate and an inner circumferential portion of the electrostatic chuck, the inner circumferential portion facing the inner circumferential region.
    Type: Application
    Filed: March 25, 2015
    Publication date: March 16, 2017
    Inventors: Ryosuke Kubota, Ren Kimura, So Tanaka, Kazuhito Kobashi
  • Publication number: 20160293708
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, and a gate electrode. The gate insulating film is provided as being in contact with the first main surface of the silicon carbide substrate. The gate electrode is provided on the gate insulating film such that the gate insulating film lies between the gate electrode and the silicon carbide substrate. In a first stress test in which a gate voltage of ?5 V is applied to the gate electrode for 100 hours at a temperature of 175° C., an absolute value of a difference between a first threshold voltage and a second threshold voltage is not more than 0.5 V, with a threshold voltage before the first stress test being defined as the first threshold voltage and a threshold voltage after the first stress test being defined as the second threshold voltage.
    Type: Application
    Filed: September 18, 2014
    Publication date: October 6, 2016
    Applicants: Sumitomo Electric Industries, Ltd., Renesas Electronics Corporation
    Inventors: Ryosuke Kubota, Shunsuke Yamada, Taku Horii, Takeyoshi Masuda, Daisuke Hamajima, So Tanaka, Shinji Kimura, Masayuki Kobayashi