Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having a first plane and a second plane; a source electrode; a drain electrode; first and second gate electrodes located; an n-type drift region and a p-type body region; n-type first and second source regions; a p-type first silicon carbide region and p-type second silicon carbide region having a p-type impurity concentration higher than the body region; first and second gate insulating layers; a p-type third silicon carbide region contacting the first silicon carbide region, a first n-type portion being located between the first gate insulating layer and the third silicon carbide region; and a p-type fourth silicon carbide region contacting the second silicon carbide region, a second n-type portion being located between the second gate insulating layer and the fourth silicon carbide region.

Abstract: A semiconductor device according to embodiments described herein includes a p-type SiC layer, a gate electrode, and a gate insulating layer between the SiC layer and the gate electrode. The gate insulating layer includes a first layer, a second layer, a first region, and a second region. The second layer is between the first layer and the gate electrode and has a higher oxygen density than the first layer. The first region is provided across the first layer and the second layer, includes a first element from F, D, and H, and has a first concentration peak of the first element. The second region is provided in the first layer, includes a second element from Ge, B, Al, Ga, In, Be, Mg, Ca, Sr, Ba, Sc, Y, La, and lanthanoid, and has a second concentration peak of the second element and a third concentration peak of C.

Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer, an insulating layer, and a region provided between the silicon carbide layer and the insulating layer, the region including a plurality of first atoms of one element from the group consisting of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi), at least some of the plurality of first atoms being four-fold coordinated atoms and/or five-fold coordinated atoms.

Abstract: A semiconductor device of an embodiment includes an SiC layer having a first and a second plane, an n-type first SiC region in the SiC layer, p-type second SiC regions between the first SiC region and the first plane, n-type third SiC regions between the second SiC regions and the first plane, a gate electrode provided between two p-type second SiC regions, a gate insulating film provided between the gate electrode and the second SiC regions, a metal layer provided between two p-type second SiC regions, and having a work function of 6.5 eV or more, and a first electrode electrically connected to the metal layer, and a second electrode, the SiC layer provided between the first electrode and the second electrode, and a part of the first SiC region is disposed between the gate insulating film and the metal layer.

Abstract: A semiconductor device according to an embodiment includes a conductive region including titanium (Ti), oxygen (O), at least one first element from zirconium (Zr) and hafnium (Hf), and at least one second element from vanadium (V), niobium (Nb), and tantalum (Ta), an n-type first SiC region, a p-type second SiC region provided between the conductive region and the n-type first SiC region, a gate electrode, and a gate insulating layer provided between the conductive region, the p-type second SiC region, the n-type first SiC region, and the gate electrode.

Abstract: A semiconductor device according to embodiments includes, a SiC substrate, SiC layer, a trench having a side face and a bottom face, a first conductivity type first SiC region, a second conductivity type second SiC region between the first SiC region and the SiC substrate, a first conductivity type third SiC region between the second SiC region and the SiC substrate, a boundary between the second SiC region and the third SiC region provided at a side of the side face, the boundary including a first region, a distance between the first region and a front face of the SiC layer increasing as a distance from the side face to the first region increasing, and distance from the side face to the first region being 0 ?m or more and 0.3 ?m or less, a gate insulating film and gate insulating film.

Abstract: A semiconductor device testing apparatus according to an embodiment includes: a first terminal and a second terminal that apply voltage to a semiconductor device; and a light source that irradiates the semiconductor device with ultraviolet light.

Abstract: A semiconductor device according to embodiments includes a p-type SiC layer having a first plane, a gate electrode, and a gate insulating layer provided between the first plane of the SiC layer and the gate electrode. The gate insulating layer includes a first layer, a second layer, and a first region. The second layer has a higher oxygen density than the first layer. The first region is provided between the first layer and the second layer and includes a first element, the first element being at least one element in the group of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), and Bi (bismuth).

Abstract: A semiconductor device according to embodiments described herein includes a p-type SiC layer, a gate electrode, and a gate insulating layer between the SiC layer and the gate electrode. The gate insulating layer includes a first layer, a second layer, a first region, and a second region. The second layer is between the first layer and the gate electrode and has a higher oxygen density than the first layer. The first region is provided across the first layer and the second layer, includes a first element from F, D, and H, and has a first concentration peak of the first element. The second region is provided in the first layer, includes a second element from Ge, B, Al, Ga, In, Be, Mg, Ca, Sr, Ba, Sc, Y, La, and lanthanoid, and has a second concentration peak of the second element and a third concentration peak of C.

Abstract: A semiconductor device according to an embodiment includes a plurality of circuit units each including a substrate, a first electrode on a first side of the substrate, a second electrode aligned with the first electrode on the first side of the substrate, a third electrode on a second side of the substrate, and a first switching element and a second switching element. The switching elements are aligned on the substrate between the first electrode, second electrode and third electrode, electrically connected in series between the first electrode and the second electrode, and having the third electrode electrically connected therebetween. In two of the adjacent circuit units, the first side of one circuit unit and the first side of the other circuit unit are adjacent to each other, and the second side of the one and the second side of the other are adjacent to each other.

Abstract: A semiconductor device of an embodiment includes a SiC layer having a surface, the surface inclined at an angle of 0° to 10° with respect to a {000-1} face or the surface having a normal line direction inclined at an angle of 80° to 90° with respect to a <000-1> direction, a gate electrode, a gate insulating layer provided between the surface and the gate electrode, and a region provided between the surface and the gate insulating layer, a maximum concentration of deuterium (D) in the region being 1×1020 cm?3 or more and a maximum concentration of hydrogen (H) in the region being 1×1019 cm?3 or less.

Abstract: A semiconductor device manufacturing method according to an embodiment includes: forming an n-type SiC layer on a SiC substrate; forming a p-type impurity region at one side of the SiC layer; exposing other side of the SiC layer by removing at least part of the SiC substrate; implanting carbon (C) ions into exposed part of the SiC layer; performing a heat treatment; forming a first electrode on the p-type impurity region; and forming a second electrode on the exposed part of the SiC layer.

Abstract: A semiconductor device testing apparatus according to an embodiment includes: a first terminal and a second terminal that apply voltage to a semiconductor device; and a light source that irradiates the semiconductor device with ultraviolet light.