Abstract: A display device includes a panel, a light source, and a display target. The panel has a transparent resin portion and a reflective film formed on a front surface of the transparent resin portion, the display target has a first display layer printed on a front surface of the reflective film and a second display layer printed on a front surface of the first display layer, the first display layer is printed so as to shield the illumination light emitted from the light source, the second display layer is printed in a color different from a color of the first display layer, an outer dimension of the second display layer is smaller than an outer dimension of the first display layer, and a border portion formed by an edge portion of the front surface of the first display layer is provided at an edge portion of the display target.

Abstract: A display device includes a panel, a light source, and a display target. The panel has a transparent resin portion and a reflective film formed on a front surface of the transparent resin portion, the display target has a first display layer printed on a front surface of the reflective film and a second display layer printed on a front surface of the first display layer, the first display layer is printed so as to shield the illumination light emitted from the light source, the second display layer is printed in a color different from a color of the first display layer, an outer dimension of the second display layer is smaller than an outer dimension of the first display layer, and a border portion formed by an edge portion of the front surface of the first display layer is provided at an edge portion of the display target.

Abstract: A switch apparatus has a wireless function and is provided with a body, a knob, which is assembled to the body and can be switch-operated, an antenna coil for communication operations, which is wound on the body, and a connecter terminal. The connecter terminal includes at least one terminal, which is provided to the body by insert molding and is bonded to the antenna coil, and at least one pin.

Abstract: To detect an abnormality in an interrupt control system without completely depending on dualization of a circuit, without the need to create a test pattern for a built-in self-test by spending time, and without considerably increasing an amount of power consumption. A test interrupt request is generated periodically using a timer or the like in an interrupt signal system from an interrupt controller to a central processing unit, the state of an interrupt request flag within the interrupt controller is checked in an interrupt processing routine, and in the case where it is detected that the same interrupt request flag is kept in a set state twice or more in succession, it is supposed that there is a high possibility that a failure has occurred in the interrupt signal system and it is considered that there is an abnormality.

Abstract: A flat cable wiring structure includes an operation mechanism that detects a physical operation made on an operating surface and outputs a detection signal, a control board, disposed facing the operating surface of the operation mechanism, that outputs a driving signal for imparting vibration to the operation mechanism on the basis of the detection signal, and a flat cable that electrically connects the operation mechanism and the control board. The flat cable includes a routing portion that extends from the operation mechanism to the control board along a movement direction of the operation mechanism. The routing portion includes a bending portion that bends at a bending angle allowing the routing portion to be routed along the control board.

Abstract: To detect an abnormality in an interrupt control system without completely depending on dualization of a circuit, without the need to create a test pattern for a built-in self-test by spending time, and without considerably increasing an amount of power consumption. A test interrupt request is generated periodically using a timer or the like in an interrupt signal system from an interrupt controller to a central processing unit, the state of an interrupt request flag within the interrupt controller is checked in an interrupt processing routine, and in the case where it is detected that the same interrupt request flag is kept in a set state twice or more in succession, it is supposed that there is a high possibility that a failure has occurred in the interrupt signal system and it is considered that there is an abnormality.

Abstract: A flat cable wiring structure includes an operation mechanism that detects a physical operation made on an operating surface and outputs a detection signal, a control board, disposed facing the operating surface of the operation mechanism, that outputs a driving signal for imparting vibration to the operation mechanism on the basis of the detection signal, and a flat cable that electrically connects the operation mechanism and the control board. The flat cable includes a routing portion that extends from the operation mechanism to the control board along a movement direction of the operation mechanism. The routing portion includes a bending portion that bends at a bending angle allowing the routing portion to be routed along the control board.

Abstract: To detect an abnormality in an interrupt control system without completely depending on dualization of a circuit, without the need to create a test pattern for a built-in self-test by spending time, and without considerably increasing an amount of power consumption. A test interrupt request is generated periodically using a timer or the like in an interrupt signal system from an interrupt controller to a central processing unit, the state of an interrupt request flag within the interrupt controller is checked in an interrupt processing routine, and in the case where it is detected that the same interrupt request flag is kept in a set state twice or more in succession, it is supposed that there is a high possibility that a failure has occurred in the interrupt signal system and it is considered that there is an abnormality.

Abstract: A switch apparatus has a wireless function and is provided with a body, a knob, which is assembled to the body and can be switch-operated, an antenna coil for communication operations, which is wound on the body, and a connecter terminal. The connecter terminal includes at least one terminal, which is provided to the body by insert molding and is bonded to the antenna coil, and at least one pin.

Abstract: To detect an abnormality in an interrupt control system without completely depending on dualization of a circuit, without the need to create a test pattern for a built-in self-test by spending time, and without considerably increasing an amount of power consumption. A test interrupt request is generated periodically using a timer or the like in an interrupt signal system from an interrupt controller to a central processing unit, the state of an interrupt request flag within the interrupt controller is checked in an interrupt processing routine, and in the case where it is detected that the same interrupt request flag is kept in a set state twice or more in succession, it is supposed that there is a high possibility that a failure has occurred in the interrupt signal system and it is considered that there is an abnormality.

Abstract: This invention provides a digital broadcasting receiving unit capable of achieving synchronization of time information between a base station and a receiving unit with reference clock without use of a crystal oscillator (VCXO) having a variable frequency. The crystal oscillator oscillates a clock of a predetermined fixed frequency. A variable digital dividing circuit divides a fixed frequency by a division ratio so as to change the division ratio. A system decoder detects reference time information from the base station. A reference counter generates time information of a receiving unit. A phase comparator detects a difference between reference time information and time information. A division ratio control circuit controls the change of the division ratio based on the difference. The reference counter generates time information based on a clock having a frequency obtained by dividing by the variable digital dividing circuit and feeds back time information to the phase comparator.

Abstract: This invention provides a digital broadcasting receiving unit capable of achieving synchronization of time information between a base station and a receiving unit with reference clock without use of a crystal oscillator (VCXO) having a variable frequency. The crystal oscillator oscillates a clock of a predetermined fixed frequency. A variable digital dividing circuit divides a fixed frequency by a division ratio so as to change the division ratio. A system decoder detects reference time information from the base station. A reference counter generates time information of a receiving unit. A phase comparator detects a difference between reference time information and time information. A division ratio control circuit controls the change of the division ratio based on the difference. The reference counter generates time information based on a clock having a frequency obtained by dividing by the variable digital dividing circuit and feeds back time information to the phase comparator.

Abstract: A data/clock recovery circuit can recover high-rate data using the data as a clock signal. It includes an edge detector, a clock selection signal generating circuit, a clock selection circuit and a synchronizing circuit. The edge detector generates edge position information using a receiver output as a clock signal. The clock selection signal generating circuit generates a clock selection signal in response to the edge position information using the receiver output as the clock signal. The clock selection circuit selects a recovered clock signal from a clock signal group in response to the clock selection signal. The synchronizing circuit synchronizes the receiver output using the recovered clock signal, and outputs it as a synchronized data signal.

Abstract: The number of pulses of a clock signal CLK-A is circularly counted in a count range from “0” to “7”, and count signals indicating count values are produced. A clock signal CLK-B having a frequency lower than that of the clock signal CLK-A is produced from count signals of “3” and “7”, and data transfer between a high speed operating block operated in synchronization with the clock signal CLK-A and a low speed operating block operated in synchronization with the clock signal CLK-B is performed in synchronization with the clock signal CLK-B to receive input serial data or transmit output serial data. When a stuff bit of universal Serial Bus is detected in the input serial data or is inserted in the output serial data, a cycle of the clock signal CLK-B is lengthened by one cycle of the clock signal CLK-A.

Abstract: Some of the circuits for executing processes on the physical layer are accommodated in a first chip that includes a link layer circuit. More specifically, an arbiter circuit composed only of a logic circuitry and having a relatively large circuit scale, and state machines, built in a control circuit, are accommodated in the first chip in the form of a control signal generation circuit. The other portions of the physical layer circuit remains in the second chip. A higher degree of integration of the first chip results in a higher degree of integration of many of the circuitry for executing processes on the physical layer.

Abstract: When a user makes the user's client computer (8) establish connection with a semiconductor intellectual property transmission service providing unit (3) by way of the Internet and then inputs desired change specifications, a semiconductor intellectual property transmission service providing unit (3) furnishes the change specifications input by the user to a semiconductor intellectual property automatically-changing unit (5). A semiconductor intellectual property data transmission unit (7) then transmits design data on changed semiconductor intellectual property output from the semiconductor intellectual property automatically-changing unit (5) to the user's client computer (8) by way of an internet communication unit (2) and the Internet.

Abstract: The number of pulses of a clock signal CLK-A is circularly counted in a count range from “0” to “7”, and count signals indicating count values are produced. A clock signal CLK-B having a frequency lower than that of the clock signal CLK-A is produced from count signals of “3” and “7”, and data transfer between a high speed operating block operated in synchronization with the clock signal CLK-A and a low speed operating block operated in synchronization with the clock signal CLK-B is performed in synchronization with the clock signal CLK-B to receive input serial data or transmit output serial data. When a stuff bit of universal Serial Bus is detected in the input serial data or is inserted in the output serial data, a cycle of the clock signal CLK-B is lengthened by one cycle of the clock signal CLK-A.

Abstract: A data/clock recovery circuit can recover high-rate data using the data as a clock signal. It includes an edge detector, a clock selection signal generating circuit, a clock selection circuit and a synchronizing circuit. The edge detector generates edge position information using a receiver output as a clock signal. The clock selection signal generating circuit generates a clock selection signal in response to the edge position information using the receiver output as the clock signal. The clock selection circuit selects a recovered clock signal from a clock signal group in response to the clock selection signal. The synchronizing circuit synchronizes the receiver output using the recovered clock signal, and outputs it as a synchronized data signal.

Abstract: A source-level debugger debugs a source program for computers using a pipeline control method. The debugger includes a not-yet-processed instruction analyzing unit for analyzing each of instructions including not-yet-process stages in a pipeline when execution of a source program is halted (or suspended) or terminated, and for acquiring information on an internal state of the pipeline. A user interface unit displays the information on the internal state of the pipeline acquired by the not-yet-processed instruction analyzing unit in a predetermined display form on the screen of a display unit.

Abstract: A sound data decoder is provided which includes a decode portion, a PCM output buffer having a plurality of fractional banks, a bank management portion supplying an address indicating a location of a writable fractional bank to the decode portion, and a PCM output portion reading and outputting, in response to the address, data from a fractional bank corresponding to that address and supplying to the bank management portion an address indicating a location of a fractional bank which is made writable.