Patents by Inventor Ryosuke Usui

Ryosuke Usui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12334235
    Abstract: A multilayer varistor of the present disclosure includes a sintered body, a first internal electrode, a second internal electrode, a first external electrode, a second external electrode, and a high-resistance layer. The first internal electrode and the second internal electrode are disposed in the sintered body. The first external electrode is disposed on a surface of the sintered body and is electrically connected to the first internal electrode. The second external electrode is disposed on the surface of the sintered body and is electrically connected to the second internal electrode. The high-resistance layer covers at least part of the surface of the sintered body, and the high-resistance layer has a surface having a plurality of cracks.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: June 17, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yuto Akiyama, Ryosuke Usui, Ken Yanai
  • Publication number: 20250142769
    Abstract: A liquid immersion cooling device includes an electronic device and a cooling medium. The electronic device includes a circuit board, a heat generator mounted on the circuit board, a heat dissipator, and a thermal conductive sheet interposed between the heat generator and the heat dissipator. The cooling medium is arranged to immerse the electronic device at least partially. At least part of the thermal conductive sheet is made of a porous material.
    Type: Application
    Filed: October 21, 2024
    Publication date: May 1, 2025
    Inventors: Youji SHIRATO, Ryosuke USUI, Naoki SAITOU, Norihiro KAWAMURA
  • Patent number: 12270502
    Abstract: Provided is a thermal insulator which can be prevented from having gaps. The thermal insulator includes a nonwoven fabric, and xerogel in interior spaces of the nonwoven fabric. The thermal insulator has a plurality of protrusions on a surface of the thermal insulator, a height of the protrusion ranges from 0.10 t to 0.25 t inclusive and a size of the protrusion at the surface of the thermal insulator ranges from t to 5 t inclusive, where t is a thickness of the thermal insulator, and pores are provided inside the thermal insulator in a region provided with the protrusions.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: April 8, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yuji Yamagishi, Ryosuke Usui, Yuuichi Abe, Shun Aota, Rikako Iwasaki
  • Publication number: 20230274864
    Abstract: A multilayer varistor according to the present disclosure includes: a sintered compact having, on a surface thereof, at least one planar portion and at least one corner portion; an internal electrode provided inside the sintered compact; a high-resistivity layer arranged to cover the at least one planar portion and the at least one corner portion of the sintered compact at least partially; and an external electrode arranged to cover the high-resistivity layer partially and electrically connected to the internal electrode. The high-resistivity layer includes: a first high-resistivity layer covering the at least one planar portion; and a second high-resistivity layer covering the at least one corner portion. The first high-resistivity layer has a larger average thickness than the second high-resistivity layer.
    Type: Application
    Filed: February 23, 2023
    Publication date: August 31, 2023
    Inventors: Yuto AKIYAMA, Ken YANAI, Masashi TAKAMURA, Yuji YAMAGISHI, Ryosuke USUI
  • Publication number: 20230274863
    Abstract: A multilayer varistor according to the present disclosure includes; a sintered compact; an internal electrode provided inside the sintered compact; a high-resistivity layer arranged to cover the sintered compact at least partially; and an external electrode arranged to cover the high-resistivity layer partially and electrically connected to the internal electrode. The high-resistivity layer includes a thinner region having a smaller thickness than a surrounding region that surrounds the thinner region.
    Type: Application
    Filed: February 23, 2023
    Publication date: August 31, 2023
    Inventors: Yuto AKIYAMA, Ken YANAI, Ryosuke USUI, Yuji YAMAGISHI, Masashi TAKAMURA
  • Publication number: 20230207159
    Abstract: A multilayer varistor includes: a sintered compact; an internal electrode provided inside the sintered compact; a high-resistivity layer arranged to cover the sintered compact at least partially and containing element Si; and an external electrode arranged to cover the high-resistivity layer partially, electrically connected to the internal electrode, and containing silver as a main component thereof. A ratio of a total mass of the alkali metals and the alkaline earth metals to a mass of the element Si in a surface region of the high-resistivity layer is equal to or less than 0.6.
    Type: Application
    Filed: December 19, 2022
    Publication date: June 29, 2023
    Inventors: Yuto AKIYAMA, Ken YANAI, Ryosuke USUI, Yuji YAMAGISHI
  • Publication number: 20230197321
    Abstract: A multilayer varistor of the present disclosure includes a sintered body, a first internal electrode, a second internal electrode, a first external electrode, a second external electrode, and a high-resistance layer. The first internal electrode and the second internal electrode are disposed in the sintered body. The first external electrode is disposed on a surface of the sintered body and is electrically connected to the first internal electrode. The second external electrode is disposed on the surface of the sintered body and is electrically connected to the second internal electrode. The high-resistance layer covers at least part of the surface of the sintered body, and the high-resistance layer has a surface having a plurality of cracks.
    Type: Application
    Filed: December 12, 2022
    Publication date: June 22, 2023
    Inventors: Yuto AKIYAMA, Ryosuke USUI, Ken YANAI
  • Publication number: 20220310291
    Abstract: A sintered body that includes semiconductor ceramic layers and an internal electrode which are alternately stacked on one another is prepared. A first external electrode is formed on a side surface of the sintered body such that the first external electrode is connected to the internal electrode. An insulating layer is formed on a surface of the sintered body by applying a glass coating over an entire of the sintered body having the formed first external electrode. The insulating layer is exposed from the first external electrode. A second external electrode is formed on the first external electrode. This method provides the produced multilayer electronic component with a stable electric connection between the internal electrodes and the external electrodes.
    Type: Application
    Filed: June 13, 2022
    Publication date: September 29, 2022
    Inventors: Ken YANAI, Tomokazu YAMAGUCHI, Yuji YAMAGISHI, Naoki MUTOU, Sayaka MATSUMOTO, Ryosuke USUI
  • Patent number: 11443883
    Abstract: A reactor device includes a coil, a magnetic core having the coil thereon, a case accommodating the coil and the magnetic core, a cooling plate fixed to the case, an insulating sheet disposed between the coil and the cooling plate, a compressible graphite sheet disposed between the coil and the cooling plate, and a screw to fix the cooling plate to the case. The case has a screw hole and an opening provided therein. The screw passes through the screw hole to fix the cooling plate to the case. The coil contacts the insulating sheet through the opening of the case. The graphite sheet contacts the cooling plate. The reactor has high cooling performance and reliability.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: September 13, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takeshi Fujii, Ryosuke Usui, Chihiro Satou
  • Patent number: 11387023
    Abstract: A sintered body that includes ceramic layers and an internal electrode which are alternately stacked on one another is prepared. A first external electrode is formed on a side surface of the sintered body such that the first external electrode is connected to the internal electrode. An insulating layer is formed on a surface of the sintered body by applying a glass coating over an entire of the sintered body having the formed first external electrode. The insulating layer is exposed from the first external electrode. A second external electrode is formed on the first external electrode. This method provides the produced multilayer electronic component with a stable electric connection between the internal electrodes and the external electrodes.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: July 12, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Ken Yanai, Tomokazu Yamaguchi, Yuji Yamagishi, Naoki Mutou, Sayaka Matsumoto, Ryosuke Usui
  • Patent number: 11384892
    Abstract: A heat insulation sheet includes a fiber sheet having spaces therein and a silica xerogel held in the spaces of the fiber sheet. The heat insulation sheet includes a thick region and a low compressible region thinner than the thick region. A compressibility of the low compressible region is equal to smaller than 5% upon having a pressure of 0.7 MPa applied to the low compressible region. This heat insulation sheet is superior in electrical insulation properties and thermal insulation properties, and secures a predetermined distance even in a case that the heat insulation sheet receives pressures from the both sides thereof, thus providing equipment with reliability.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: July 12, 2022
    Assignee: PANASONIC INIELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yuuichi Abe, Chihiro Satou, Ryosuke Usui
  • Patent number: 10453776
    Abstract: A semiconductor device includes a semiconductor module including a semiconductor element, a passive element, a cooling member, a first conductive member and a second conductive member. The cooling member is disposed between the semiconductor module and the passive element. And a first conductive member and a second conductive member electrically connect the semiconductor module and the passive element. Furthermore, two or more aspects of at least one of the first conductive member and the second conductive member face the cooling member.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: October 22, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Ryosuke Usui, Tetsuzo Ueda
  • Patent number: 10297516
    Abstract: A semiconductor device includes a semiconductor element, a base, and an outer packaging resin. The base has a mounting surface, on which the semiconductor element is mounted, and a groove provided around the semiconductor element on the mounting surface. An outer packaging resin covers the semiconductor element and the base, and is fixed to the base by filling the groove. A bottom of the groove includes a first recess-projection having a first amplitude and a first repetition interval along an extending direction of the groove. The first recess-projection includes a second recess-projection having a second amplitude smaller than the first amplitude and a second repetition interval shorter than the first repetition interval along the extending direction of the groove.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: May 21, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Masayuki Nagamatsu, Shinya Marumo, Junichi Kimura, Tatsuya Kunisato, Ryosuke Usui
  • Patent number: 10211144
    Abstract: This semiconductor device includes a semiconductor element mounted on a metal layer, first to third connection terminals that are provided on the semiconductor element, a first bus bar bonded to the first connection terminal, and a second bus bar bonded to the second connection terminal. The semiconductor element is bonded to the metal layer, and the first to third connection terminals are disposed on a top surface of the semiconductor element. One end of the first bus bar is bonded to the first connection terminal, another end of the first bus bar is an output unit, one end of the second bus bar is bonded to the second connection terminal, and another end of the second bus bar is bonded to the metal layer. A first surface of the semiconductor element and the second bus bar are at an identical potential.
    Type: Grant
    Filed: July 4, 2016
    Date of Patent: February 19, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shinichi Kohda, Junichi Kimura, Ryosuke Usui, Tomohide Ogura, Atsushi Watanabe
  • Patent number: 9439285
    Abstract: In the upper surface of a metallic substrate, a region near the central part of the metallic substrate is surrounded by a rectangle having dotted sides electrically separate the interior and exterior of the rectangle. Each dot of the sides is formed of a pillared insulating resin that penetrates from the upper surface to the lower surface of the metallic substrate. Oxide films are so formed as to fill in the spaces between adjacent cylinders of insulating resins and the surrounding of the cylinders. That is, a separation layer is formed of the pillared insulating resins and the oxide films that fill up the spaces between the pillared insulating resins as well as their vicinities.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: September 6, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Keishi Kato, Osamu Tabata, Yoshio Okayama, Ryosuke Usui
  • Patent number: 9129933
    Abstract: A semiconductor module has a first substrate and a second substrate placed opposite to the first substrate. A first semiconductor element is provided such that the high-heat main face of the first semiconductor faces the second substrate and is thermally connected to the second substrate via a wiring layer. A second semiconductor element is provided such that the high-heat main face of the second semiconductor faces the first substrate and is thermally connected to the first substrate via another wiring layer. The emitter electrode of the first semiconductor element and the collector electrode of the second semiconductor element are electrically connected to each other via a heat spreader.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: September 8, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tetsuya Yamamoto, Ryosuke Usui
  • Patent number: 9024446
    Abstract: Conventional printed circuit boards had a problem of being inferior in heat-radiation characteristic, and metal-core printed circuit boards adopted to improve the heat-radiation characteristic had problems in having low rigidity and a tendency to bend. The ductility of the metal can be obstructed, and the metal protected; by covering substantially the whole area of the front and back sides of the metal core, consisting of metal as the main material, with a first ceramic film and a second ceramic film that obstruct the ductility of the aforementioned metal-core; and covering each of the ceramic films with insulated resin films, to cover the fragility of these ceramics.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: May 5, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Ryosuke Usui, Yusuke Igarashi, Yasunori Inoue, Mayumi Nakasato, Masayuki Nagamatsu, Yasuhiro Kohara
  • Publication number: 20140085834
    Abstract: In the upper surface of a metallic substrate, a region near the central part of the metallic substrate is surrounded by a rectangle having dotted sides electrically separate the interior and exterior of the rectangle. Each dot of the sides is formed of a pillared insulating resin that penetrates from the upper surface to the lower surface of the metallic substrate. Oxide films are so formed as to fill in the spaces between adjacent cylinders of insulating resins and the surrounding of the cylinders. That is, a separation layer is formed of the pillared insulating resins and the oxide films that fill up the spaces between the pillared insulating resins as well as their vicinities.
    Type: Application
    Filed: November 27, 2013
    Publication date: March 27, 2014
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Keishi KATO, Osamu TABATA, Yoshio OKAYAMA, Ryosuke USUI
  • Publication number: 20140077354
    Abstract: A semiconductor module has a first substrate and a second substrate placed opposite to the first substrate. A first semiconductor element is provided such that the high-heat main face of the first semiconductor faces the second substrate and is thermally connected to the second substrate via a wiring layer. A second semiconductor element is provided such that the high-heat main face of the second semiconductor faces the first substrate and is thermally connected to the first substrate via another wiring layer. The emitter electrode of the first semiconductor element and the collector electrode of the second semiconductor element are electrically connected to each other via a heat spreader.
    Type: Application
    Filed: November 27, 2013
    Publication date: March 20, 2014
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Tetsuya YAMAMOTO, Ryosuke USUI
  • Patent number: 8656581
    Abstract: A method for fabricating a circuit apparatus includes forming a wiring layer, a conductive layer, and a first insulating layer on the wiring substrate, removing the conductive layer in an opening of the first insulating layer so as to expose the wiring layer, forming a gold plating layer on the wiring layer, removing the first insulating layer and the conductive layer, forming a second insulating layer on the wiring substrate, the second insulating layer having an opening through which the gold plating and adjacent wiring layers are exposed, and electrically connecting a circuit element to the gold plating layer.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: February 25, 2014
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Makoto Murai, Yasuhiro Kohara, Ryosuke Usui