Patents by Inventor Ryota Asada

Ryota Asada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11482489
    Abstract: According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: October 25, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Shingo Nakajima, Ryota Asada, Hidenobu Nagashima, Masayuki Akou
  • Publication number: 20200373237
    Abstract: According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.
    Type: Application
    Filed: August 11, 2020
    Publication date: November 26, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Shingo Nakajima, Ryota Asada, Hidenobu Nagashima, Masayuki Akou
  • Patent number: 10777501
    Abstract: According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: September 15, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shingo Nakajima, Ryota Asada, Hidenobu Nagashima, Masayuki Akou
  • Publication number: 20190287894
    Abstract: According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.
    Type: Application
    Filed: July 3, 2018
    Publication date: September 19, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Shingo NAKAJIMA, Ryota Asada, Hidenobu Nagashima, Masayuki Akou