Patents by Inventor Ryota Katsumata

Ryota Katsumata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190312012
    Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.
    Type: Application
    Filed: April 22, 2019
    Publication date: October 10, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masayoshi TAGAMI, Ryota KATSUMATA, Jun IIJIMA, Tetsuya SHIMIZU, Takamasa USUI, Genki FUJITA
  • Patent number: 10418378
    Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: September 17, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
  • Patent number: 10381374
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 13, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masayoshi Tagami, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
  • Publication number: 20190164979
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Application
    Filed: January 30, 2019
    Publication date: May 30, 2019
    Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
  • Patent number: 10297578
    Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: May 21, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masayoshi Tagami, Ryota Katsumata, Jun Iijima, Tetsuya Shimizu, Takamasa Usui, Genki Fujita
  • Publication number: 20190148404
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Application
    Filed: January 11, 2019
    Publication date: May 16, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masaru KITO, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Publication number: 20190096899
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, first, second, third, and fourth insulating bodies, first and second columnar portions. The stacked body includes a conductive layer and an insulating layer stacked alternately. The first, second, third and fourth insulating bodies, the first and second columnar portions are provided inside the stacked body. The second insulating body is at a position different from the first insulating body. The third insulating body is between the first and second insulating bodies. The fourth insulating body is between the first and second insulating bodies, and includes portions contacting the third insulating body and being separated from each other with the third insulating body interposed. The first columnar portion is between the first and fourth insulating bodies. The second columnar portion is between the second and fourth insulating bodies. The first and second columnar portions include a semiconductor layer.
    Type: Application
    Filed: April 9, 2018
    Publication date: March 28, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masayoshi Tagami, Ryota Katsumata, Toru Matsuda, Yu Hirotsu, Naoki Yamamoto
  • Publication number: 20190096908
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.
    Type: Application
    Filed: November 29, 2018
    Publication date: March 28, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshiaki FUKUZUMI, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
  • Publication number: 20190088676
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.
    Type: Application
    Filed: March 5, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masayoshi TAGAMI, Jun IIJIMA, Ryota KATSUMATA, Kazuyuki HIGASHI
  • Publication number: 20190074284
    Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.
    Type: Application
    Filed: October 31, 2018
    Publication date: March 7, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshihiro AKUTSU, Ryota KATSUMATA
  • Patent number: 10211219
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: February 19, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Patent number: 10199387
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: February 5, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
  • Patent number: 10163931
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: December 25, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
  • Publication number: 20180358368
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Application
    Filed: August 17, 2018
    Publication date: December 13, 2018
    Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
  • Patent number: 10134751
    Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: November 20, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshihiro Akutsu, Ryota Katsumata
  • Publication number: 20180261623
    Abstract: A semiconductor memory device includes a first memory cell array layer includes a first memory cell array region, in which memory cells are 3-dimensionally arrayed, and a first and second surface wiring layer connected to the memory cells. A second memory cell array layer includes second memory cell array region, in which memory cells are 3-dimensionally arrayed, and a third and fourth surface wiring layer connected to the second plurality of memory cells. The first memory cell array layer and the second memory cell array layer are bonded to each other such that the second surface wiring layer and the third surface wiring layer face each other and are bonded to each other. The first and second memory cell array regions overlap each other as viewed from a direction orthogonal to a layer plane.
    Type: Application
    Filed: August 28, 2017
    Publication date: September 13, 2018
    Inventors: Kazuyuki HIGASHI, Kazumichi TSUMURA, Ryota KATSUMATA, Fumitaka ARAI
  • Publication number: 20180261575
    Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.
    Type: Application
    Filed: September 15, 2017
    Publication date: September 13, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Masayoshi TAGAMI, Ryota Katsumata, Jun Iijima, Tetsuya Shimizu, Takamasa Usui, Genki Fujita
  • Patent number: 10074667
    Abstract: A semiconductor memory device includes a first memory cell array layer includes a first memory cell array region, in which memory cells are 3-dimensionally arrayed, and a first and second surface wiring layer connected to the memory cells. A second memory cell array layer includes second memory cell array region, in which memory cells are 3-dimensionally arrayed, and a third and fourth surface wiring layer connected to the second plurality of memory cells. The first memory cell array layer and the second memory cell array layer are bonded to each other such that the second surface wiring layer and the third surface wiring layer face each other and are bonded to each other. The first and second memory cell array regions overlap each other as viewed from a direction orthogonal to a layer plane.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: September 11, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuyuki Higashi, Kazumichi Tsumura, Ryota Katsumata, Fumitaka Arai
  • Publication number: 20180240814
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.
    Type: Application
    Filed: April 24, 2018
    Publication date: August 23, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KIDOH, Masaru KITO, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Hideaki AOCHI
  • Patent number: 10056403
    Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: August 21, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase