Patents by Inventor Ryota Katsumata
Ryota Katsumata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9601503Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: GrantFiled: March 8, 2016Date of Patent: March 21, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Publication number: 20170062441Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: ApplicationFiled: November 11, 2016Publication date: March 2, 2017Inventors: Tomoo HISHIDA, Sadatoshi MURAKAMI, Ryota KATSUMATA, Masao IWASE
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Patent number: 9502299Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.Type: GrantFiled: September 2, 2014Date of Patent: November 22, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tomoo Hishida, Sadatoshi Murakami, Ryota Katsumata, Masao Iwase
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Publication number: 20160254271Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.Type: ApplicationFiled: May 11, 2016Publication date: September 1, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiro AKUTSU, Ryota Katsumata
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Publication number: 20160240554Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: ApplicationFiled: April 28, 2016Publication date: August 18, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KIDOH, Masaru KITO, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Hideaki AOCHI
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Publication number: 20160190152Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: ApplicationFiled: March 8, 2016Publication date: June 30, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KITO, Masaru KIDOH, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Junya MATSUNAMI, Tomoko FUJIWARA, Hideaki AOCHI, Ryouhei KlRISAWA, Yoshimasa MIKAJIRI, Shigeto OOTA
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Patent number: 9373634Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The second insulating film seals the hole near an interface of the insulating layer and the select gate. The second insulating film is provided on a side wall of the channel body with a space left in the hole above the select gate. The method can include burying a semiconductor film in the space, in addition, forming a conductive film in contact with the channel body.Type: GrantFiled: May 8, 2015Date of Patent: June 21, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuru Sato, Masaru Kito, Megumi Ishiduki, Ryota Katsumata
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Patent number: 9362298Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.Type: GrantFiled: March 12, 2015Date of Patent: June 7, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiro Akutsu, Ryota Katsumata
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Patent number: 9356042Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: GrantFiled: March 25, 2015Date of Patent: May 31, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
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Patent number: 9318503Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: GrantFiled: August 24, 2015Date of Patent: April 19, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Patent number: 9312134Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: GrantFiled: January 8, 2014Date of Patent: April 12, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Publication number: 20160079250Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.Type: ApplicationFiled: March 12, 2015Publication date: March 17, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiro AKUTSU, Ryota Katsumata
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Publication number: 20160079069Abstract: According to one embodiment, a memory device includes: a first insulating film, a first electrode, a second insulating film, and a second electrode being stacked in a multilayer body, and an end of the first electrode extending outside a region directly under the second electrode in an end of the multilayer body; a pillar piercing the first electrode and the second electrode; a memory film between the first electrode and the pillar, between the second electrode and the pillar, and being capable of storing a charge; an insulating film on the end of the multilayer body; and a contact piercing the insulating film, and being connected to the end of the first electrode film. A first portion connected to the contact in the first electrode film includes a metal or a metal nitride. A second portion surrounding the memory film in the first electrode film includes silicon.Type: ApplicationFiled: July 28, 2015Publication date: March 17, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Tsuneo UENAKA, Ryota Katsumata
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Publication number: 20160071866Abstract: According to one embodiment, the first columnar part includes a first channel body and a first charge storage film. The second columnar part includes a second channel body and a second charge storage film. The second columnar part is provided adjacent in the first direction to the first columnar part. The connection part connects a lower end of the first channel body and a lower end of the second channel body. Each of the source layers is connected to an upper end of the first columnar part. Each of the bit lines is connected to an upper end of the second columnar part of every (n+1)-th memory string of a plurality of memory strings arranged in the first direction.Type: ApplicationFiled: August 5, 2015Publication date: March 10, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Yoshiro SHIMOJO, Masaru KIDOH, Masaru KITO, Ryota KATSUMATA, Yoshihiro YANAI
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Publication number: 20150372006Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: ApplicationFiled: May 29, 2015Publication date: December 24, 2015Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
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Publication number: 20150364489Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: ApplicationFiled: August 24, 2015Publication date: December 17, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki FUKUZUMI, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Patent number: 9196627Abstract: According to an aspect of the invention, a first insulating layer is buried in a first trench provided in at least one of an interstice between first and second semiconductor pillars, a side surface portion of the first semiconductor pillar opposed to the second semiconductor pillar, and a side surface portion of the second semiconductor pillar opposed to the first semiconductor pillar. A first trench penetrates each stack from an uppermost portion of the stack to a first conductive layer in a lowermost portion of the stack. The first trench is arranged away from a first connection portion. Each of the first conductive layers in contact with the first insulating layer includes a silicide layer.Type: GrantFiled: March 5, 2014Date of Patent: November 24, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Konno, Ryota Katsumata, Yoshiaki Fukuzumi
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Patent number: 9147575Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: GrantFiled: January 8, 2014Date of Patent: September 29, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Patent number: RE45840Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.Type: GrantFiled: July 9, 2014Date of Patent: January 12, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Ryota Katsumata, Hideaki Aochi, Hiroyasu Tanaka, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Patent number: RE45890Abstract: According to one embodiment, in the case of performing an operation for increasing a threshold voltage of a first transistor or a third transistor, a control circuit is configured to apply a first voltage to a bit line, and apply a second voltage greater than the first voltage to a gate of a second transistor, thereby rendering the second transistor in a conductive state to transfer the first voltage to a second semiconductor layer, and then apply a program voltage to a gate of the first transistor or the third transistor to store a charge in a second charge storage layer.Type: GrantFiled: October 23, 2014Date of Patent: February 16, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kiyotaro Itagaki, Yoshiaki Fukuzumi, Yoshihisa Iwata, Ryota Katsumata