Patents by Inventor Ryota NIHEI

Ryota NIHEI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240176439
    Abstract: Provided is a display antenna including a display including a plurality of light emitters arranged in a grid, an antenna array having an antenna assembly in which a plurality of patch antennas through which light in a wavelength band of a visible region is transmitted is disposed in a grid, the antenna array being disposed to be superimposed on the display, and a phase shifter disposed in a gap region sandwiched between the plurality of light emitters, connected to at least one of the plurality of patch antennas, and configured to shift a signal to be transmitted and received.
    Type: Application
    Filed: November 22, 2023
    Publication date: May 30, 2024
    Applicant: NEC Corporation
    Inventors: Ryota NIHEI, Junichi FUNADA, Kenji WAKAFUJI, Kazuyuki HAYASHI, Kohei YOSHIDA, Shingo WATANABE, Kazushi SUGYO, Masakazu ONO, Fujio OKUMURA
  • Publication number: 20240178576
    Abstract: Provided is an antenna device including an antenna array including a plurality of patch antennas arrayed in a grid, a first switch group including a first switch disposed on a wiring line connecting two adjacent patch antennas, and a second switch group including a second switch disposed on a wiring line between an antenna assembly formed by at least four adjacent patch antennas and a signal source connected to at least one patch antenna constituting the antenna assembly.
    Type: Application
    Filed: November 22, 2023
    Publication date: May 30, 2024
    Applicant: NEC Corporation
    Inventors: Ryota NIHEI, Junichi FUNADA, Kenji WAKAFUJI, Kazuyuki HAYASHI, Kohei YOSHIDA, Shingo WATANABE, Kazushi SUGYO, Masakazu ONO, FUJIO OKUMURA
  • Publication number: 20240098995
    Abstract: According to one embodiment, a semiconductor storage device has first and second gate electrodes extending in one direction. A first semiconductor layer is between the first gate electrode and the second gate electrode. A second semiconductor layer is also between the first semiconductor layer and the second gate electrode but separated from the first semiconductor layer. A third semiconductor layer is between the first gate electrode and the second gate electrode but is spaced from the first semiconductor layer by a gap. A first charge trapping layer is between the first gate electrode and the first semiconductor layer. A second charge trapping layer is between the second gate electrode and the second semiconductor layer. A third charge trapping layer is between the first gate electrode and the third semiconductor layer.
    Type: Application
    Filed: March 3, 2023
    Publication date: March 21, 2024
    Inventors: Ryota NIHEI, Koji MATSUO
  • Publication number: 20240090239
    Abstract: A semiconductor device includes a metal layer disposed above a transistor on a first substrate. The metal layer includes a first region extending in a first direction and a second region that has a width in the first direction smaller than the first region and protrudes from the first region in a second direction, and has a first corner portion having an angle larger than 180° as viewed in a third direction between a proximal end portion of the second region and the first region. The metal layer includes a first portion that is disposed within the first region and has a lower surface at a first height, and a second portion that is disposed within the second region and has a lower surface at a second height lower than the first height.
    Type: Application
    Filed: March 1, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Kiichi TACHI, Ryota NIHEI, Yoshikazu HOSOMURA
  • Publication number: 20170068757
    Abstract: the design data and the simulation data includes a comparator, an identification code assigning unit, and a short-circuit determining unit. The comparator is configured to compare design data of a semiconductor device with simulation data of the semiconductor device to extract areas different therebetween. With reference to the extracted areas extracted by the comparator, the identification code assigning unit is configured to assign different identification codes to the extracted areas corresponding to different conductors The short-circuit determining unit determines whether the extracted areas to which the different identification codes have been assigned are within a predetermined distance or not to determine a short circuit position in the semiconductor device.
    Type: Application
    Filed: March 8, 2016
    Publication date: March 9, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Ryota NIHEI
  • Publication number: 20170018564
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body provided on the substrate and including multiple electrode layers separately stacked with each other, a semiconductor film, a charge storage film provided between the semiconductor film and the multiple electrode layers, and a first insulating film provided between the semiconductor film and the charge storage film, extending in the stacking direction, and having a bottom surface contacting the substrate. The semiconductor film is provided integrally with the substrate in the stacked body, and extends in a stacking direction of the stacked body. An orientation of a crystal structure of the semiconductor film is equal to an orientation of a crystal structure of the substrate.
    Type: Application
    Filed: November 9, 2015
    Publication date: January 19, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Ryota NIHEI
  • Publication number: 20150076702
    Abstract: A semiconductor device including a semiconductor substrate having a hook-up region; wirings extending in a first direction above the semiconductor substrate and being aligned with a first spacing between one another, every two wirings forming pairs of wirings, each pair having a first portion being bent in a second direction different from the first direction in the hook-up region, the wirings of each pair being spaced from one another by a first spacing, the pairs being spaced from one another by a second spacing greater than the first spacing; and fringe patterns each being formed on a first side of each of the wirings of each of the pairs, the first side facing the second spacing.
    Type: Application
    Filed: August 1, 2014
    Publication date: March 19, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Naoyuki IIDA, Satoshi Nagashima, Shoichi Miyazaki, Ryota Nihei
  • Publication number: 20150060859
    Abstract: In accordance with an embodiment, an evaluation sample includes a substrate and a polycrystalline film on the substrate. The polycrystalline film has crystal grains. A specific orientation plane is exposed on the surface of each crystal grain. The orientation planes exhibit random angles to the surface of the substrate.
    Type: Application
    Filed: January 6, 2014
    Publication date: March 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Ryota NIHEI