Patents by Inventor Ryota Senda

Ryota Senda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9991349
    Abstract: Certain embodiments provide a semiconductor device including a semiconductor substrate, a semiconductor element, and wiring. The semiconductor element has an electrode provided on a surface of the semiconductor substrate. The electrode includes a junction layer joined to the surface of the semiconductor substrate, a diffusion-suppressing layer provided on the junction layer, and a pad layer provided on the diffusion-suppressing layer. The wiring is provided on a back surface of the semiconductor substrate and on an inner surface of a through hole which penetrates the semiconductor substrate immediately below the electrode. The wiring is electrically connected to the electrode.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: June 5, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryota Senda
  • Publication number: 20160056273
    Abstract: Certain embodiments provide a semiconductor device including a semiconductor substrate, a semiconductor element, and wiring. The semiconductor element has an electrode provided on a surface of the semiconductor substrate. The electrode includes a junction layer joined to the surface of the semiconductor substrate, a diffusion-suppressing layer provided on the junction layer, and a pad layer provided on the diffusion-suppressing layer. The wiring is provided on a back surface of the semiconductor substrate and on an inner surface of a through hole which penetrates the semiconductor substrate immediately below the electrode. The wiring is electrically connected to the electrode.
    Type: Application
    Filed: August 7, 2015
    Publication date: February 25, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Ryota SENDA
  • Patent number: 9082836
    Abstract: A field effect transistor includes a stacked body, a source electrode, a drain electrode, a gate electrode, a dielectric layer and a silicon nitride layer. The stacked layer has a heterojunction made of a nitride semiconductor. The source and drain electrodes are provided on a surface of the stacked body. The gate electrode is provided on the surface of the stacked body between the source and the drain electrodes, and has a field plate portion. The dielectric layer is provided so as to cover an intersection line of a first side surface of the gate electrode and the surface of the stacked body. The silicon nitride layer is provided so as to cover a region between the source electrode and the gate electrode and a region between the dielectric layer and the drain electrode. The field plate portion protrudes from the first side surface.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: July 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryota Senda
  • Publication number: 20140252435
    Abstract: A semiconductor device concerning an embodiment is provided with a plate-like semiconductor substrate, electrode pads, electrode connecting conductors, and a source electrode back pad. The semiconductor substrate has a first cutout section in a first side, and has a second cutout section and a third cutout section in a second side. A drain electrode connecting conductor is provided in the first cutout section, and one end thereof touches the drain electrode pad, and the other end thereof is exposed in a back surface of the semiconductor substrate. A gate electrode connecting conductor is provided in the third cutout section, and one end thereof touches the gate electrode pad, and the other end thereof is exposed in the back of the semiconductor substrate. A source electrode connecting conductor is provided in the second cutout section, and one end thereof touches the source electrode pad.
    Type: Application
    Filed: September 9, 2013
    Publication date: September 11, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Ryota SENDA
  • Patent number: 8735943
    Abstract: A semiconductor device includes a semiconductor layer, an insulating film, a gate electrode, a drain electrode, and a source electrode. The semiconductor layer includes an active layer and is formed on a semi-insulating semiconductor substrate, and a tapered recess area having an inclined sidewall is formed on a surface of the semiconductor layer. The insulating film is formed on the semiconductor layer and has a through hole for exposing the recess area. The through hole has a tapered sidewall which is inclined at an angle smaller than the sidewall of the recess area. The gate electrode is formed so as to fill the recess area and the through hole. The drain electrode and the source electrode are formed at positions on opposite sides of the recess area on the semiconductor layer.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: May 27, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Senda, Hisao Kawasaki
  • Publication number: 20130341680
    Abstract: A field effect transistor includes a stacked body, a source electrode, a drain electrode, a gate electrode, a dielectric layer and a silicon nitride layer. The stacked layer has a heterojunction made of a nitride semiconductor. The source and drain electrodes are provided on a surface of the stacked body. The gate electrode is provided on the surface of the stacked body between the source and the drain electrodes, and has a field plate portion. The dielectric layer is provided so as to cover an intersection line of a first side surface of the gate electrode and the surface of the stacked body. The silicon nitride layer is provided so as to cover a region between the source electrode and the gate electrode and a region between the dielectric layer and the drain electrode. The field plate portion protrudes from the first side surface.
    Type: Application
    Filed: December 27, 2012
    Publication date: December 26, 2013
    Inventor: Ryota SENDA
  • Publication number: 20130093006
    Abstract: A semiconductor device includes a semiconductor layer, an insulating film, a gate electrode, a drain electrode, and a source electrode. The semiconductor layer includes an active layer and is formed on a semi-insulating semiconductor substrate, and a tapered recess area having an inclined sidewall is formed on a surface of the semiconductor layer. The insulating film is formed on the semiconductor layer and has a through hole for exposing the recess area. The through hole has a tapered sidewall which is inclined at an angle smaller than the sidewall of the recess area. The gate electrode is formed so as to fill the recess area and the through hole. The drain electrode and the source electrode are formed at positions on opposite sides of the recess area on the semiconductor layer.
    Type: Application
    Filed: August 30, 2012
    Publication date: April 18, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryota Senda, Hisao Kawasaki