Abstract: A resistance variable memory apparatus (100) of the present invention includes a current suppressing element (116) which is connected in series with each resistance variable layer (114) and whose threshold voltage is VF, and is configured to apply a first voltage V1 to a first wire (WL) associated with a selected nonvolatile memory element, apply a second voltage V2 to a second wire (BL) associated with the selected nonvolatile memory element, apply a third voltage V3 to a first wire (WL) which is not associated with the selected nonvolatile memory element and apply a fourth voltage V4 to a second wire (BL) which is not associated with the selected memory element when writing data or reading data, wherein V2?V3<V5 and V5<V4?V1 are satisfied and (V1?V4)<VF or (V3?V2)<VF is satisfied when V5=(V1+V2)/2 is a fifth voltage V5.

Abstract: Memory cells (MC) are formed at intersections of bit lines (BL) extending in the X direction and word lines (WL) extending in the Y direction. A plurality of basic array planes sharing the word lines (WL), each formed for a group of bit lines (BL) aligned in the Z direction, are arranged side by side in the Y direction. In each basic array plane, bit lines in even layers and bit lines in odd layers are individually connected in common. Each of selection switch elements (101 to 104) controls switching of electrical connection/non-connection between the common-connected even layer bit line and a global bit line (GBL), and each of selection switch elements (111 to 114) control switching of connection/non-connection between the common-connected odd layer bit line and the global bit line (GBL).

Abstract: An oscillation circuit 10 outputs oscillation clocks 100 different in phase, and a four-phase clock generation circuit 20 generates a four-phase clock 200 based on a difference in phase between the oscillation clocks 100. A four-phase clock transfer control circuit 50 controls whether to transfer the four-phase clock 200 in accordance with a signal CP_EN, and a pump circuit 60 generates a boosted voltage based on the transferred four-phase clock. A time period of delay Tos between clocks included in the four-phase clock 200 is generated based on the difference in phase between the oscillation clocks 100, and therefore always in a proportional relationship with a cycle (Tosc) of the oscillation clocks 100. Accordingly, even if the cycle (Tosc) is changed due to operating conditions, and therefore a time period of charge transfer (Ttr) can be uniquely determined.

Abstract: A memory cell transistor array is composed of a plurality of memory cells having three or more threshold voltage distribution states in a single electric charge accumulation portion. A program sequence control circuit associates each piece of data included in a data set composed of a plurality of data values with any threshold voltage distribution of the three or more threshold voltage distributions, to store the data in the memory cell, and when rewriting the data stored in the memory cell, shifting threshold voltage distributions used for data storage in one direction to perform the data rewrite operation.

Abstract: An oscillation circuit 10 outputs oscillation clocks 100 different in phase, and a four-phase clock generation circuit 20 generates a four-phase clock 200 based on a difference in phase between the oscillation clocks 100. A four-phase clock transfer control circuit 50 controls whether to transfer the four-phase clock 200 in accordance with a signal CP_EN, and a pump circuit 60 generates a boosted voltage based on the transferred four-phase clock. A time period of delay Tos between clocks included in the four-phase clock 200 is generated based on the difference in phase between the oscillation clocks 100, and therefore always in a proportional relationship with a cycle (Tosc) of the oscillation clocks 100. Accordingly, even if the cycle (Tosc) is changed due to operating conditions, and therefore a time period of charge transfer (Ttr) can be uniquely determined.

Abstract: A semiconductor memory device having a memory array is provided. A read unit reads information stored in a memory cell. A step-up unit steps up an externally supplied voltage, and supplies the stepped-up voltage to the memory cell. A start control unit has the step-up unit start the stepping up after a read cycle begins. A detection unit detects that the stepped-up voltage has reached a predetermined level, and has the read unit start the reading upon the detection. A stop control unit has the step-up unit stop the stepping up when a time period required for the reading has elapsed since the detection. With this construction, the time taken for stepping up the voltage supplied to the memory cell is minimized in accordance with the time taken for the reading. Hence the current consumption is reduced when compared with the case where the step-up time is set unnecessarily long.

Abstract: A semiconductor memory device having a memory array is provided. A read unit reads information stored in a memory cell. A step-up unit steps up an externally supplied voltage, and supplies the stepped-up voltage to the memory cell. A start control unit has the step-up unit start the stepping up after a read cycle begins. A detection unit detects that the stepped-up voltage has reached a predetermined level, and has the read unit start the reading upon the detection. A stop control unit has the step-up unit stop the stepping up when a time period required for the reading has elapsed since the detection. With this construction, the time taken for stepping up the voltage supplied to the memory cell is minimized in accordance with the time taken for the reading. Hence the current consumption is reduced when compared with the case where the step-up time is set unnecessarily long.