Patents by Inventor Ryotaro Kamikawai

Ryotaro Kamikawai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5184027
    Abstract: A clock signal supply system provides for automatic accurate phase adjustment of clock signals. The system includes an oscillator that produces clock signals and a reference generator that generates a reference signal that has a predetermined relationship with respect to the clock signals produced by the oscillator. At each location where the clock signal is to be received, an adjusting circuit is provided to adjust the phase of the received clock signals. Such an adjusting circuit may include a variable delay circuit which receives the clock signal and produces an output which is constituted by the clock signal having a varied delay, to the remainder of the attached circuits. Further, the output of the variable delay is fed back to a phase difference detection circuit. The reference signal is second input to the phase difference detection circuit.
    Type: Grant
    Filed: April 22, 1991
    Date of Patent: February 2, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Noboru Masuda, Ryotaro Kamikawai, Masayoshi Yagyu, Masakazu Yamamoto, Hiroyuki Itoh, Tatsuya Saito
  • Patent number: 5151617
    Abstract: A superconducting logic circuit is configured by using two kinds of input-output type quantum flux parametrons (QFP), that is, a periodically excited input-output type QFP and an arbitrarily excited input-output type QFP. The periodically excited QFP is excited by periodically varying exciting magnetic flux to amplify a binary magnetic flux. The arbitrarily excited QFP is excited by magnetic flux output signals of upstream QFPs.
    Type: Grant
    Filed: March 6, 1991
    Date of Patent: September 29, 1992
    Assignees: Research Development Corporation of Japan, Ryotaro Kamikawai
    Inventors: Eiichi Goto, Willy Hioe, Mutsumi Hosoya, Ryotaro Kamikawai
  • Patent number: 5146119
    Abstract: A switching circuit which comprises a digital circuit formed of a superconductor, a transmission line connected to the digital circuit through magnetic coupling, and a resistor element disposed in the transmission line for differentiating the output of the digital circuit.
    Type: Grant
    Filed: December 28, 1989
    Date of Patent: September 8, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Ryotaro Kamikawai, Akira Masaki
  • Patent number: 4806111
    Abstract: A connector structure comprising an electrically conductive plate having a plurality of through holes formed therein, an electrically insulated film formed on the inner wall of at least one of the through holes, an electrically conductive film formed on the inner wall of at least one other through hole, and an electrically conductive material of a low melting point provided within the through holes. The low melting point material provided in the through holes whose inner walls are coated with an electrically insulating film is insulated from the electrically conductive plate and such through holes may serve to receive signal propagating pins.
    Type: Grant
    Filed: November 3, 1986
    Date of Patent: February 21, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Masaaki Nishi, Moritoshi Yasunaga, Ryotaro Kamikawai
  • Patent number: 4626889
    Abstract: A semiconductor integrated circuit structure including a semiconductor substrate having a large area adapted for a large scale integration, a circuit formed in the substrate for generating a pair of complementary signals, a pair of common potential level layers with an electrically insulating layer interposed therebetween, the common potential level layers being formed above and being electrically insulated from the substrate, and a pair of electric conductor pattern layers formed in the insulating layer for conducting the pair of complementary signals. The electric conductor pattern layers are arranged so as to be overlapped with each other in a direction substantially perpendicular to the large area substrate and so as to be substantially parallel with the large area substrate.
    Type: Grant
    Filed: December 18, 1984
    Date of Patent: December 2, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Masakazu Yamamoto, Akira Masaki, Ryotaro Kamikawai