Abstract: A processor includes a cache memory that holds data from a main storage device. The processor includes a first control unit that controls acquisition of data, and that outputs an input/output request that requests the transfer of the target data. The processor includes a second control unit that controls the cache memory, that determines, when an instruction to transfer the target data and a response output by the first processor on the basis of the input/output request that has been output to the first processor is received, whether the destination of the response is the processor, and that outputs, to the first control unit when the second control unit determines that the destination of the response is the processor, the response and the target data with respect to the input/output request.

Abstract: A processor includes a first processing unit that has a first memory and performs processing, a second processing unit that performs processing, a second memory that holds status information specifying a status of data held in the first memory, and a control unit that outputs a request for reading out the data of the first address to the first processing unit upon receiving a first access request for data of a first address from the second processing unit when first status information of the data of the first address indicates that the data of the first address is held in the first memory in an exclusive state or an owned state and that allows the second processing unit to access data of the first address included at the second memory upon receiving a no-data-modification notification indicating the data of the first address is not modified by the first processing unit.