Patents by Inventor Ryotaro Yagi
Ryotaro Yagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10115792Abstract: A semiconductor device is disclosed. The semiconductor device includes an insulating layer formed selectively on a semiconductor layer; a lower electrode, formed on the insulating layer, having an end portion at a position spaced apart by a predetermined distance inward from a periphery of the insulating layer; a dielectric film formed on the lower electrode; an upper electrode, formed on the dielectric film, facing the lower electrode with the dielectric film interposed between the upper electrode and the lower electrode; and a passivation film, formed to cover the insulating layer, starting from the end portion of the lower electrode and extending toward the periphery of the insulating layer. The passivation film includes an insulating material having an etching selectivity with respect to the insulating layer.Type: GrantFiled: February 10, 2016Date of Patent: October 30, 2018Assignee: ROHM CO., LTD.Inventors: Shinya Yamazaki, Ryotaro Yagi
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Publication number: 20160163795Abstract: A semiconductor device is disclosed. The semiconductor device includes an insulating layer formed selectively on a semiconductor layer; a lower electrode, formed on the insulating layer, having an end portion at a position spaced apart by a predetermined distance inward from a periphery of the insulating layer; a dielectric film formed on the lower electrode; an upper electrode, formed on the dielectric film, facing the lower electrode with the dielectric film interposed between the upper electrode and the lower electrode; and a passivation film, formed to cover the insulating layer, starting from the end portion of the lower electrode and extending toward the periphery of the insulating layer. The passivation film includes an insulating material having an etching selectivity with respect to the insulating layer.Type: ApplicationFiled: February 10, 2016Publication date: June 9, 2016Applicant: ROHM CO., LTD.Inventors: Shinya YAMAZAKI, Ryotaro YAGI
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Patent number: 9281391Abstract: A semiconductor device is disclosed. The semiconductor device includes an insulating layer formed selectively on a semiconductor layer; a lower electrode, formed on the insulating layer, having an end portion at a position spaced apart by a predetermined distance inward from a periphery of the insulating layer; a dielectric film formed on the lower electrode; an upper electrode, formed on the dielectric film, facing the lower electrode with the dielectric film interposed between the upper electrode and the lower electrode; and a passivation film, formed to cover the insulating layer, starting from the end portion of the lower electrode and extending toward the periphery of the insulating layer. The passivation film includes an insulating material having an etching selectivity with respect to the insulating layer.Type: GrantFiled: April 15, 2014Date of Patent: March 8, 2016Assignee: ROHM CO., LTD.Inventors: Shinya Yamazaki, Ryotaro Yagi
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Publication number: 20140306275Abstract: A semiconductor device is disclosed. The semiconductor device includes an insulating layer formed selectively on a semiconductor layer; a lower electrode, formed on the insulating layer, having an end portion at a position spaced apart by a predetermined distance inward from a periphery of the insulating layer; a dielectric film formed on the lower electrode; an upper electrode, formed on the dielectric film, facing the lower electrode with the dielectric film interposed between the upper electrode and the lower electrode; and a passivation film, formed to cover the insulating layer, starting from the end portion of the lower electrode and extending toward the periphery of the insulating layer. The passivation film includes an insulating material having an etching selectivity with respect to the insulating layer.Type: ApplicationFiled: April 15, 2014Publication date: October 16, 2014Applicant: ROHM CO., LTD.Inventors: Shinya YAMAZAKI, Ryotaro YAGI
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Patent number: 8709939Abstract: A multilevel interconnect structure in a semiconductor device and methods for fabricating the same are described. The multilevel interconnect structure in the semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.Type: GrantFiled: October 2, 2012Date of Patent: April 29, 2014Assignees: Semiconductor Technology Academic Research Center, National University Corporation Tohoku UniversityInventors: Junichi Koike, Yoshito Fujii, Jun Iijima, Noriyoshi Shimizu, Kazuyoshi Maekawa, Koji Arita, Ryotaro Yagi, Masaki Yoshimaru
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Patent number: 8384208Abstract: A semiconductor device capable of improving a mechanical strength of a porous silica film while inhibiting a film located on a lower layer of the porous silica film from deterioration is obtained. This semiconductor device includes an organic film formed on a semiconductor substrate, an ultraviolet light permeation suppressive film, formed on a surface of the organic film, composed of a material which is difficult to be permeable by ultraviolet light, and a first porous silica film formed on a surface of the ultraviolet light permeation suppressive film.Type: GrantFiled: July 12, 2007Date of Patent: February 26, 2013Assignees: Sanyo Electric Co., Ltd., NEC Corporation, Rohn Co., Ltd.Inventors: Yoshinori Shishida, Shinichi Chikaki, Ryotaro Yagi, Kazuo Kohmura, Hirofumi Tanaka
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Patent number: 8304908Abstract: A multilevel interconnect structure in a semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.Type: GrantFiled: March 19, 2009Date of Patent: November 6, 2012Assignees: Semiconductor Technology Academic Research Center, National University Corporation Tohoku UniversityInventors: Junichi Koike, Yoshito Fujii, Jun Iijima, Noriyoshi Shimizu, Kazuyoshi Maekawa, Koji Arita, Ryotaro Yagi, Masaki Yoshimaru
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Patent number: 8237221Abstract: The semiconductor device according to the present invention includes a semiconductor layer, a trench formed by digging the semiconductor layer from the surface thereof, a gate insulating film formed on the inner surface of the trench, and a gate electrode made of silicon embedded in the trench through the gate insulating film. The gate electrode has a high-conductivity portion formed to cover the gate insulating film with a relatively high conductivity and a low-conductivity portion formed on a region inside the high-conductivity portion with a relatively low conductivity.Type: GrantFiled: August 22, 2011Date of Patent: August 7, 2012Assignee: Rohm Co., Ltd.Inventors: Ryotaro Yagi, Isamu Nishimura, Takahisa Yamaha
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Publication number: 20110298044Abstract: The semiconductor device according to the present invention includes a semiconductor layer, a trench formed by digging the semiconductor layer from the surface thereof, a gate insulating film formed on the inner surface of the trench, and a gate electrode made of silicon embedded in the trench through the gate insulating film. The gate electrode has a high-conductivity portion formed to cover the gate insulating film with a relatively high conductivity and a low-conductivity portion formed on a region inside the high-conductivity portion with a relatively low conductivity.Type: ApplicationFiled: August 22, 2011Publication date: December 8, 2011Inventors: Ryotaro YAGI, Isamu Nishimura, Takahisa Yamaha
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Patent number: 8044491Abstract: The semiconductor device according to the present invention includes a lower electrode made of a metallic material, a capacitance film made of an insulating material and laminated on the lower electrode, an upper electrode made of a metallic material, opposed to the lower electrode through the capacitance film, and having an outline smaller than that of the lower electrode in plan view along the opposed direction, and a protective film made of the same material as that of the capacitance film and laminated on the upper electrode.Type: GrantFiled: July 15, 2010Date of Patent: October 25, 2011Assignee: Rohm Co., Ltd.Inventors: Ryotaro Yagi, Yuichi Nakao, Isamu Nishimura
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Patent number: 8022472Abstract: The semiconductor device according to the present invention includes a semiconductor layer, a trench formed by digging the semiconductor layer from the surface thereof, a gate insulating film formed on the inner surface of the trench, and a gate electrode made of silicon embedded in the trench through the gate insulating film. The gate electrode has a high-conductivity portion formed to cover the gate insulating film with a relatively high conductivity and a low-conductivity portion formed on a region inside the high-conductivity portion with a relatively low conductivity.Type: GrantFiled: December 3, 2008Date of Patent: September 20, 2011Assignee: Rohm Co., Ltd.Inventors: Ryotaro Yagi, Isamu Nishimura, Takahisa Yamaha
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Patent number: 8022497Abstract: A semiconductor device capable of preventing an interlayer dielectric film from deterioration resulting from a liquid such as a chemical solution penetrating into the interlayer dielectric film and recovering the interlayer dielectric film from deterioration with a prescribed gas is obtained. This semiconductor device comprises a first insulating film formed on a substrate and a first gas-liquid separation film, formed on at least a part of the surface of the first insulating film, composed of a material hardly permeable by a liquid and easily permeable by a gas.Type: GrantFiled: February 28, 2007Date of Patent: September 20, 2011Assignees: Sanyo Electric Co., Ltd., NEC Corporation, Rohm Co., Ltd.Inventors: Yoshinori Shishida, Shinichi Chikaki, Ryotaro Yagi
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Publication number: 20100283125Abstract: The semiconductor device according to the present invention includes a lower electrode made of a metallic material, a capacitance film made of an insulating material and laminated on the lower electrode, an upper electrode made of a metallic material, opposed to the lower electrode through the capacitance film, and having an outline smaller than that of the lower electrode in plan view along the opposed direction, and a protective film made of the same material as that of the capacitance film and laminated on the upper electrode.Type: ApplicationFiled: July 15, 2010Publication date: November 11, 2010Applicant: ROHM CO., LTD.Inventors: Ryotaro Yagi, Yuichi Nakao, Isamu Nishimura
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Patent number: 7781863Abstract: The semiconductor device according to the present invention includes a lower electrode made of a metallic material, a capacitance film made of an insulating material and laminated on the lower electrode, an upper electrode made of a metallic material, opposed to the lower electrode through the capacitance film, and having an outline smaller than that of the lower electrode in plan view along the opposed direction, and a protective film made of the same material as that of the capacitance film and laminated on the upper electrode.Type: GrantFiled: January 7, 2008Date of Patent: August 24, 2010Assignee: ROHM Co., Ltd.Inventors: Ryotaro Yagi, Yuichi Nakao, Isamu Nishimura
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Patent number: 7646101Abstract: An insulating layer is formed on a semiconductor substrate, and has a through hole for via. A porous silica layer has a trench for interconnection communicating to the through hole for via, and is formed on the insulating layer in contact therewith. A conductive layer is formed in the through hole for via and in the trench for interconnection. The insulating layer is formed from a material containing carbon, hydrogen, oxygen, and silicon, and having absorption peak attributed to Si—CH3 bond in a range from at least 1260 cm?1 to at most 1280 cm?1 (around 1274 cm?1) when measured with FT-IR. Thus, a semiconductor device having a porous insulating layer in which depth of the trench for interconnection is readily controlled, a dielectric constant is low, and increase in leakage current is less likely, as well as a manufacturing method thereof can be obtained.Type: GrantFiled: March 28, 2007Date of Patent: January 12, 2010Assignees: Rohm Co., Ltd., NEC Corporation, Sanyo Electric Co., Ltd.Inventors: Ryotaro Yagi, Shinichi Chikaki, Yoshinori Shishida
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Publication number: 20090236747Abstract: A multilevel interconnect structure in a semiconductor device comprises a first insulating layer (2) formed on a semiconductor wafer (1), a Cu interconnect layer (4) formed on the first insulating layer (2), a second insulating layer (6) formed on the Cu interconnect layer (4), and a metal oxide layer (5) formed at an interface between the Cu interconnect layer (4) and the second insulating layer (6). The metal oxide layer (5) is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer (4) and then heat-treating the plated layer in an oxidizing atmosphere.Type: ApplicationFiled: March 19, 2009Publication date: September 24, 2009Applicants: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER, NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITYInventors: Junichi Koike, Yoshito Fujii, Jun Iijima, Noriyoshi Shimizu, Kazuyoshi Maekawa, Koji Arita, Ryotaro Yagi, Masaki Yoshimaru
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Publication number: 20090140330Abstract: The semiconductor device according to the present invention includes a semiconductor layer, a trench formed by digging the semiconductor layer from the surface thereof, a gate insulating film formed on the inner surface of the trench, and a gate electrode made of silicon embedded in the trench through the gate insulating film. The gate electrode has a high-conductivity portion formed to cover the gate insulating film with a relatively high conductivity and a low-conductivity portion formed on a region inside the high-conductivity portion with a relatively low conductivity.Type: ApplicationFiled: December 3, 2008Publication date: June 4, 2009Applicant: ROHM CO., LTD.Inventors: Ryotaro Yagi, Isamu Nishimura, Takahisa Yamaha
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Publication number: 20080164565Abstract: The semiconductor device according to the present invention includes a lower electrode made of a metallic material, a capacitance film made of an insulating material and laminated on the lower electrode, an upper electrode made of a metallic material, opposed to the lower electrode through the capacitance film, and having an outline smaller than that of the lower electrode in plan view along the opposed direction, and a protective film made of the same material as that of the capacitance film and laminated on the upper electrode.Type: ApplicationFiled: January 7, 2008Publication date: July 10, 2008Applicant: ROHM CO., LTD.Inventors: Ryotaro Yagi, Yuichi Nakao, Isamu Nishimura
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Publication number: 20080050566Abstract: A semiconductor device capable of improving a mechanical strength of a porous silica film while inhibiting a film located on a lower layer of the porous silica film from deterioration is obtained. This semiconductor device includes an organic film formed on a semiconductor substrate, an ultraviolet light permeation suppressive film, formed on a surface of the organic film, composed of a material which is difficult to be permeable by ultraviolet light, and a first porous silica film formed on a surface of the ultraviolet light permeation suppressive film.Type: ApplicationFiled: July 12, 2007Publication date: February 28, 2008Inventors: Yoshinori Shishida, Shinichi Chikaki, Ryotaro Yagi, Kazuo Kohmura, Hirofumi Tanaka
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Publication number: 20070269977Abstract: In a formation method of a copper damascene multilayer wiring in a semiconductor integrated circuit device, after performing an oxidation process on a surface of copper, a heating process of 300° C. to 400° C. is performed in a reducing gas atmosphere, or a plasma annealing process is performed in a reducing gas plasma atmosphere.Type: ApplicationFiled: May 16, 2007Publication date: November 22, 2007Applicants: NEC CORPORATION, ROHM CO., LTD, SANYO ELECTRONIC CO., ULVAC, INC, RENESAS TECHNOLOGY CORPInventors: Shinichi Chikaki, Ryotaro Yagi, Yoshinori Shishida, Hirofumi Tanaka, Takahiro Nakayama, Yoko Uchida