Abstract: A management system includes a plurality of resources configured to be electrically connected to an external power supply, and a management device configured to manage the resources. The management device includes a planning unit and a management unit. The planning unit is configured to determine a power balancing plan of each of the resources by using first information on a use schedule of each of the resources and second information indicating a magnitude of an environmental load in a process of generating electric power to be supplied by the external power supply. The management unit is configured to manage the resources to cause each of the resources to operate according to the power balancing plan or a modified power balancing plan in power balancing of the external power supply.

Abstract: This numerical control apparatus 5 controls the operation of a machine tool 2 on the basis of a numerical control program, generates, for a robot control device 6 that controls the operation of a robot 3 and a transfer device 4 which moves the robot 3, a robot command for moving a control axis of the robot 3 and a travel axis command for moving a travel axis of the transfer device 4, and inputs the generated commands to the robot control device 6. The numerical control apparatus 5 comprises: a coordinate value management unit 55 that acquires, respectively as additional axis reference coordinate values and robot reference coordinate values, coordinate values of the travel axis of the transfer device 4 and the control axis of the robot 3 acquired by the robot control device 6; and a command generation unit 56 that generates the robot command and the travel axis command on the basis of the numerical control program, the robot reference coordinate values, and travel axis reference coordinate values.

Abstract: A numerical control device 5 is provided with: a program preprocessing unit 54 for generating, on the basis of analysis results for each block of a numerical control program, a block robot instruction recognizable by a robot control device 6, and block information associated with the block robot instruction; a robot instruction storage unit 523 for storing the block robot instruction and the block information generated by the program preprocessing unit 54; a program execution management unit 58 for reading in the block information specified by a program execution instruction and the block robot instruction associated with the block information, from the robot instruction storage unit 523; and a first communication unit 59 for transmitting the block robot instruction read in by the program execution management unit 58 to the robot control device 6.

Abstract: A numerical control system 1 comprises a numerical control device 5 that generates a machine tool command signal as a command directed to a machine tool 2, in accordance with a machine tool numerical control program, and generates a robot command signal as a command directed to a robot 3, in accordance with a robot numerical control program, and a robot control device 6 that is capable of communicating with the numerical control device 5, and controls an operation of the robot 3 on the basis of the robot command signal. The robot control device 6 acquires form information that is information necessary for identifying the form of the robot 3, and transmits the form information to the numerical control device 5. The numerical control device 5 generates a robot command signal on the basis of the form information transmitted from the robot control device 6 and the robot numerical control program.

Abstract: This numerical control system 1 comprises: a numerical control device 5 that generates a machine-tool command signal, which is a command to a machine tool 2, in accordance with a machine-tool numerical control program, and generates a robot command signal, which is a command to a robot 3, in accordance with a robot numerical control program described on the basis of a robot coordinate system; and a robot control device 6 that controls an operation of the robot 3 on the basis of the robot command signal. The robot control device 6 acquires a coordinate value of the robot 3 in the robot coordinate system, and transmits the coordinate value as a reference coordinate value to the numerical control device 5. The numerical control device 5 generates the robot command signal on the basis of the reference coordinate value transmitted from the robot control device 6 and the robot numerical control program.

Abstract: A vessel propulsion apparatus includes an engine main body including a crankshaft that is rotatable about a rotation axis extending in the up-down direction, auxiliary machinery mounted on the engine main body, a bracket that couples the auxiliary machinery to the engine main body, and an engine cowling that houses the engine main body, the auxiliary machinery, and the bracket. The bracket includes a first mounting portion mounted on the engine main body, a second mounting portion mounted on the auxiliary machinery, a coupling portion coupling the first mounting portion and the second mounting portion, and a holding portion provided in the coupling portion. The holding portion of the bracket holds piping.

Abstract: A vessel propulsion apparatus includes an engine main body including a crankshaft that is rotatable about a rotation axis extending in the up-down direction, auxiliary machinery mounted on the engine main body, a bracket that couples the auxiliary machinery to the engine main body, and an engine cowling that houses the engine main body, the auxiliary machinery, and the bracket. The bracket includes a first mounting portion mounted on the engine main body, a second mounting portion mounted on the auxiliary machinery, a coupling portion coupling the first mounting portion and the second mounting portion, and a holding portion provided in the coupling portion. The holding portion of the bracket holds piping.

Abstract: A semiconductor device manufacturing method capable of making in-plane temperature distribution on a wafer uniform at heat treatment time. Before heat treatment is performed by irradiating the wafer with lamp light from the side of a device formed area where semiconductor devices are to be formed, an SiN film with certain thickness the reflection factor of which is equal to the average reflection factor of the device formed area is formed in an edge portion outside the device formed area. By doing so, reflection factors on the surface of the wafer irradiated with lamp light can be made uniform and uniform temperature distribution on the wafer can be obtained at heat treatment time. As a result, in-plane variations in the characteristics of semiconductor devices on the wafer can be made small and high-quality semiconductor devices can be manufactured.

Abstract: A semiconductor device manufacturing method capable of making in-plane temperature distribution on a wafer uniform at heat treatment time. Before heat treatment is performed by irradiating the wafer with lamp light from the side of a device formed area where semiconductor devices are to be formed, an SiN film with certain thickness the reflection factor of which is equal to the average reflection factor of the device formed area is formed in an edge portion outside the device formed area. By doing so, reflection factors on the surface of the wafer irradiated with lamp light can be made uniform and uniform temperature distribution on the wafer can be obtained at heat treatment time. As a result, in-plane variations in the characteristics of semiconductor devices on the wafer can be made small and high-quality semiconductor devices can be manufactured.

Abstract: A semiconductor device manufacturing method capable of making in-plane temperature distribution on a wafer uniform at heat treatment time. Before heat treatment is performed by irradiating the wafer with lamp light from the side of a device formed area where semiconductor devices are to be formed, an SiN film with certain thickness the reflection factor of which is equal to the average reflection factor of the device formed area is formed in an edge portion outside the device formed area. By doing so, reflection factors on the surface of the wafer irradiated with lamp light can be made uniform and uniform temperature distribution on the wafer can be obtained at heat treatment time. As a result, in-plane variations in the characteristics of semiconductor devices on the wafer can be made small and high-quality semiconductor devices can be manufactured.

Abstract: There is provided a method of manufacturing semiconductor device comprising removing an organic substance from a semiconductor surface having an oxide film thereon, the semiconductor surface being formed to have a line width of 50 nm or less; removing the oxide film from the semiconductor surface; drying the semiconductor surface without using an organic solvent; and forming a silicide layer on the semiconductor surface after drying the semiconductor surface.

Abstract: The semiconductor device fabrication method comprises the step of forming gate electrode 20 on a semiconductor substrate 10 with a gate insulation film 18 formed therebetween; the step of implanting dopants in the semiconductor substrate 10 with the gate electrode 20 as the mask to form dopant diffused regions 28, 36; the step of forming a silicon oxide film 38 on the semiconductor substrate 10, covering the gate electrodes 20; anisotropically etching the silicon oxide film 38 to form sidewall spacers 42 including the silicon oxide film 38 on the side walls of the gate electrode 20. In the step of forming a silicon oxide film 38, the silicon oxide film 38 is formed by thermal CVD at a 500-580° C. film forming temperature, using bis (tertiary-butylamino) silane and oxygen as raw materials.

Abstract: The semiconductor device fabrication method comprises the step of forming gate electrode 20 on a semiconductor substrate 10 with a gate insulation film 18 formed therebetween; the step of implanting dopants in the semiconductor substrate 10 with the gate electrode 20 as the mask to form dopant diffused regions 28, 36; the step of forming a silicon oxide film 38 on the semiconductor substrate 10, covering the gate electrodes 20; anisotropically etching the silicon oxide film 38 to form sidewall spacers 42 including the silicon oxide film 38 on the side walls of the gate electrode 20. In the step of forming a silicon oxide film 38, the silicon oxide film 38 is formed by thermal CVD at a 500–580° C. film forming temperature, using bis(tertiary-butylamino)silane and oxygen as raw materials.

Abstract: A semiconductor device manufacturing method capable of making in-plane temperature distribution on a wafer uniform at heat treatment time. Before heat treatment is performed by irradiating the wafer with lamp light from the side of a device formed area where semiconductor devices are to be formed, an SiN film with certain thickness the reflection factor of which is equal to the average reflection factor of the device formed area is formed in an edge portion outside the device formed area. By doing so, reflection factors on the surface of the wafer irradiated with lamp light can be made uniform and uniform temperature distribution on the wafer can be obtained at heat treatment time. As a result, in-plane variations in the characteristics of semiconductor devices on the wafer can be made small and high-quality semiconductor devices can be manufactured.

Abstract: A semiconductor device manufacture method has the steps of: (a) forming a polishing stopper layer over a semiconductor substrate; (b) etching the semiconductor substrate to form a trench; (c) forming a first liner insulating layer of silicon oxide over the surface of the trench; (d) forming a second liner insulating layer of silicon nitride over the first liner insulating layer, the second liner insulating layer having a thickness of at least 20 nm or at most 8 nm; (e1) depositing a third liner insulating layer of silicon oxide over the second liner insulating layer by plasma CVD at a first bias; and (e2) depositing an isolation layer of silicon oxide by plasma CVD at a second bias higher than the first bias, the isolation layer burying a recess defined by the third liner insulating layer.

Abstract: A method of producing a semiconductor device is disclosed that is able to reduce fluctuations of a sheet resistance of a silicide layer in the semiconductor device formed by a salicide process. When depositing a titanium nitride film on a cobalt film in the salicide process, the thickness of the titanium nitride film is set to be sufficiently small so that a nano-grain structure or an amorphous structure is formed in the titanium nitride film. In the titanium nitride film, the titanium composition is enriched.

Abstract: There is provided a method of manufacturing semiconductor device comprising removing an organic substance from a semiconductor surface having an oxide film thereon, the semiconductor surface being formed to have a line width of 50 nm or less; removing the oxide film from the semiconductor surface; drying the semiconductor surface without using an organic solvent; and forming a silicide layer on the semiconductor surface after drying the semiconductor surface.

Abstract: The semiconductor device fabrication method comprises the step of forming gate electrode 20 on a semiconductor substrate 10 with a gate insulation film 18 formed therebetween; the step of implanting dopants in the semiconductor substrate 10 with the gate electrode 20 as the mask to form dopant diffused regions 28, 36; the step of forming a silicon oxide film 38 on the semiconductor substrate 10, covering the gate electrodes 20; anisotropically etching the silicon oxide film 38 to form sidewall spacers 42 including the silicon oxide film 38 on the side walls of the gate electrode 20. In the step of forming a silicon oxide film 38, the silicon oxide film 38 is formed by thermal CVD at a 500-580° C. film forming temperature, using bis(tertiary-butylamino)silane and oxygen as raw materials.

Abstract: A semiconductor device manufacture method has the steps of: (a) forming a polishing stopper layer over a semiconductor substrate; (b) etching the semiconductor substrate to form a trench; (c) forming a first liner insulating layer of silicon oxide over the surface of the trench; (d) forming a second liner insulating layer of silicon nitride over the first liner insulating layer, the second liner insulating layer having a thickness of at least 20 nm or at most 8 nm; (e1) depositing a third liner insulating layer of silicon oxide over the second liner insulating layer by plasma CVD at a first bias; and (e2) depositing an isolation layer of silicon oxide by plasma CVD at a second bias higher than the first bias, the isolation layer burying a recess defined by the third liner insulating layer.