Patents by Inventor Ryou Yonezu

Ryou Yonezu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Master slice integrated circuit having a memory region
    Patent number: 5172210
    Abstract: A gate array chip (33) has an array (41) of strip-shaped active areas (18) formed on a semiconductor substrate (40). Wiring-dedicated areas (34), each having capacity for two to four wires, are provided between respective adjacent pairs of the active areas (18). In a logic circuit region, one or more active areas (18) are employed as wiring areas. In memory blocks, wiring is performed by employing only the wiring-dedicated areas (34). A master slice integrated circuit manufactured from the gate array chip (33) has a high degree of integration and high operating speed.
    Type: Grant
    Filed: April 26, 1991
    Date of Patent: December 15, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Ryou Yonezu
  • Master slice integrated circuit having a memory region
    Patent number: 5108942
    Abstract: A gate array chip (33) has an array (41) of strip-shaped active areas (18) formed on a semiconductor substrate (40). Wiring-dedicated areas (34), each having capacity for two to four wires, are provided between respective adjacent pairs of the active areas (18). In a logic circuit region, one or more active areas (18) are employed as wiring areas. In memory blocks, wiring is performed by employing only the wiring-dedicated areas (34). A master slice integrated circuit manufactured from the gate array chip (33) has a high degree of integration and high operating speed.
    Type: Grant
    Filed: May 3, 1989
    Date of Patent: April 28, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Ryou Yonezu
  • Master slice integrated circuit having a memory region
    Patent number: 4849932
    Abstract: A gate array chip (33) has an array (41) of strip-shaped active areas (18) formed on a semiconductor substrate (40). Wiring-dedicated areas (34), each having capacity for two to four wires, are provided between respective adjacent pairs of the active areas (18). In a logic circuit region, one or more active areas (18) are employed as wiring areas. In memory blocks, wiring is performed by employing only the wiring-dedicated areas (34). A master slice integrated circuit manufactured from the gate array chip (33) has a high degree of integration and high operating speed.
    Type: Grant
    Filed: March 8, 1988
    Date of Patent: July 18, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Ryou Yonezu