Abstract: A process for forming an array of FATMOS transistors serving as memory cells of a NAND cell type EEPROM. A multi-layered structure is provided on a substrate with two stacked conductive layers insulated by an intermediate insulative layer, the first or inner conductive layer being insulated by a first insulative layer from the substrate, the second or outer conductive layer being covered with a second insulative layer. The second insulative layer is etched to define a first array of etched layer portions. A photoresist layer is deposited and etched to define a second array of layer portions, each of which is positioned between two neighboring ones of the first array of layer portions. The multi-layered structure is etched with the first and second layer portions being as a mask, to thereby form an array of a plurality of pairs of insulated gate electrodes above the substrate.

Abstract: A semiconductor nonvolatile memory device according to the invention comprises a first cell block having with a current path and a plurality of memory cells, a second cell block having with a current path and a plurality of memory cells, the current path of the second cell block has an end connected to a corresponding end of the current path of the first cell block, a first line electrically connected to the other end of the current path of the first cell block, and a second line electrically connected to the other end of the current path of the second cell block. The first and second lines are made to operate a bit line and a source line, or vise versa, depending on which one of said cell blocks is selected for data retrieval.

Abstract: An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range.

Abstract: The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask.

Abstract: An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range.

Abstract: A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.

Abstract: A NAND cell type EEPROM has parallel data transmission lines formed above a substrate, and a memory cell section including a plurality of NAND type cell units containing a NAND type cell unit that is associated with a certain bit line of the bit lines. This NAND type cell unit has a series-circuit of a preselected number of data storage transistors with control gates, and a selection transistor. A substrate voltage-stabilizing layer is insulatively provided above the substrate and positioned in the field area in adjacent to the certain bit line. The conductive layer is connected to the substrate by a contact portion so that the substrate voltage can be constantly set to a preselected voltage potential of a fixed value during the NAND type cell unit is being subjected to the write and erase modes.

Abstract: An erasable programmable read-only memory with a NAND cell structure including NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected is series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line.

Abstract: An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into NAND cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain. These semiconductor layers are formed in a P type well layer formed in a surface area of a substrate. The well layer serves as a surface breakdown prevention layer. During a data erase mode data stored in all the memory cells are erased simultaneously. During the data write mode subsequent to the erase mode, when a certain NAND cell block is selected, memory cells in the NAND cell block are subjected to data writing in sequence.

Abstract: An erasable programmable read-only memory with NAND cell structure is disclosed which includes NAND cell blocks each of which has a selection transistor connected to a corresponding bit line and a series array of memory cell transistors. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data erase mode all the memory cells are simultaneously erased by applying a "H" level potential to the control gates of the memory cells and a "L" level potential to the bit lines. Prior to such a simultaneous erase, charges are removed from charge accumulation layers of the memory cells so that the threshold values of the memory cells are initialized. The threshold initialization is performed on the series-arrayed memory cell transistors in the NAND cell block in sequence.