Abstract: A semiconductor integrated circuit device includes a first clock domain having a plurality of first flip-flops which is configured to operate with a high-speed clock; a second clock domain having a plurality of second flip-flops, composed of a third flip-flop and a plurality of fourth flip-flops, which is configured to operate with a low-speed clock; and a test clock supplying section configured to supply, at a time of delay fault test for the second clock domain, a test clock based on the high-speed clock to the third flip-flop to which data from the first clock domain is input, and not to supply the test clock to the plurality of fourth flip-flops.

Abstract: A semiconductor integrated circuit device includes a first clock domain having a plurality of first flip-flops which is configured to operate with a high-speed clock; a second clock domain having a plurality of second flip-flops, composed of a third flip-flop and a plurality of fourth flip-flops, which is configured to operate with a low-speed clock; and a test clock supplying section configured to supply, at a time of delay fault test for the second clock domain, a test clock based on the high-speed clock to the third flip-flop to which data from the first clock domain is input, and not to supply the test clock to the plurality of fourth flip-flops.

Abstract: It is an object of the present invention to provide a data switching method capable of impartially selecting a plurality of input ports by a simple circuit configuration. The data switching method according to the present invention includes an up-counter, a down-counter, a counter selecting circuit for selecting either of a counted value by the up-counter or a counted value by the down-counter, a port selecting circuit for selecting one of a plurality of input ports based on an output from the counter selecting circuit, and a buffer for accumulating a packet supplied from the input port selected by the port selecting circuit. The port selecting circuit alternately selects the up-counter and the down-counter to switch the ascending order and the descending order of the import priority of the input ports at every time the packet is imported, thereby impartially selecting each of the input ports.

Abstract: There is provided a compact ATM switch. Each of the bit values of at least one of counters for counting the number of ATM cells in a cell buffer is set to be “H” when the at least one of counters is preset.

Abstract: A semiconductor integrated circuit device has a plurality of functional blocks. Each of the plurality of functional blocks comprises a DLL circuit for outputting a clock signal, at least one wiring portion for receiving the clock signal at one end thereof, and at least one load circuit for receiving the clock signal from the DLL circuit via the wiring portion. The DLL circuit receives a reference clock signal and a wiring portion and outputs the clock signal so that the phase difference between the reference clock signal and the second clock signal is a predetermined value. Thus, clock skew is reduced even if there is variation due to process.