Patents by Inventor Ryouichi Furukawa

Ryouichi Furukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040214428
    Abstract: Conductive layers are formed in the trenches made in an insulating film in the following manner. First, an amorphous silicon film 26A is deposited in the trenches 25 made in a silicon oxide film 24. A photoresist film 30 is then formed on the amorphous silicon film 26A by means of spin coating. Then, exposure light is applied to the entire surface of the photoresist film 30, thereby exposing to light those parts of the photoresist film 30 which lie outside the trenches 25. The other parts of the photoresist film 30, which lie in the trenches 25 are not exposed to light because the light reaching them is inadequate. Further, the photoresist film 30 is developed thereby removing those parts of the film 30 which lie outside the trenches 25 and which have been exposed to light. Thereafter, those parts of the amorphous silicon film 26A, which lie outside the trenches 25, are removed by means of dry etching using, as a mask, the unexposed parts of the photoresist film 30 which remain in the trenches 25.
    Type: Application
    Filed: May 17, 2004
    Publication date: October 28, 2004
    Applicants: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Ryouichi Furukawa, Kazuyuki Suko, Masayuki Hiranuma, Koichi Saitoh, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Maki Shimoda
  • Publication number: 20040195611
    Abstract: A silicon oxide film on which a capacitor of a semiconductor integrated circuit device is formed is formed by the plasma CVD method at a temperature of 450° C. to 700° C. In this semiconductor integrated circuit device, a memory cell formed of a MISFET for data transfer and a capacitor is formed in a memory cell forming area, and an n channel MISFET and a p channel MISFET constituting a logic circuit is formed in a logic circuit forming area. As a result, the amount of degassing from the silicon oxide film can be reduced. Therefore, the growth of silicon grains on a surface of the silicon film constituting a lower electrode of the capacitor is not hindered by the degassing, and it becomes possible to increase the capacitance. Also, the step of a heat treatment for removing the moisture and the like after forming the silicon oxide film can be omitted, and it becomes possible to prevent the deterioration of the property of the MISFET.
    Type: Application
    Filed: April 21, 2004
    Publication date: October 7, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Tsuyoshi Fujiwara, Takeshi Saikawa, Ryouichi Furukawa, Masato Kunitomo
  • Patent number: 6770528
    Abstract: Conductive layers are formed in the trenches made in an insulating film in the following manner. First, an amorphous silicon film 26A is deposited in the trenches 25 made in a silicon oxide film 24. A photoresist film 30 is then formed on the amorphous silicon film 26A by means of spin coating. Then, exposure light is applied to the entire surface of the photoresist film 30, thereby exposing to light those parts of the photoresist film 30 which lie outside the trenches 25. The other parts of the photoresist film 30, which lie in the trenches 25 are not exposed to light because the light reaching them is inadequate. Further, the photoresist film 30 is developed thereby removing those parts of the film 30 which lie outside the trenches 25 and which have been exposed to light. Thereafter, those parts of the amorphous silicon film 26A, which lie outside the trenches 25, are removed by means of dry etching using, as a mask, the unexposed parts of the photoresist film 30 which remain in the trenches 25.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: August 3, 2004
    Assignees: Hitachi ULSI Systems Co., Ltd., Renesas Technology Corp.
    Inventors: Ryouichi Furukawa, Kazuyuki Suko, Masayuki Hiranuma, Koichi Saitoh, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Maki Shimoda
  • Patent number: 6746913
    Abstract: A silicon oxide film on which a capacitor of a semiconductor integrated circuit device is formed is formed by the plasma CVD method at a temperature of 450° C. to 700° C. In this semiconductor integrated circuit device, a memory cell formed of a MISFET for data transfer and a capacitor is formed in a memory cell forming area, and an n channel MISFET and a p channel MISFET constituting a logic circuit is formed in a logic circuit forming area. As a result, the amount of degassing from the silicon oxide film can be reduced. Therefore, the growth of silicon grains on a surface of the silicon film constituting a lower electrode of the capacitor is not hindered by the degassing, and it becomes possible to increase the capacitance. Also, the step of a heat treatment for removing the moisture and the like after forming the silicon oxide film can be omitted, and it becomes possible to prevent the deterioration of the property of the MISFET.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: June 8, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Tsuyoshi Fujiwara, Takeshi Saikawa, Ryouichi Furukawa, Masato Kunitomo
  • Patent number: 6717202
    Abstract: A first silicon film is so formed as to extend along the inner surface of trenches 52 formed in a silicon oxide film 50, an oxide film is formed on the surface of the first silicon film, and a second amorphous silicon film is further deposited. Heat-treatment is applied to the surface of the second amorphous silicon film for seeding silicon nuclei and for promoting grain growth, and a granular silicon crystal 57 is grown from the second amorphous silicon film. In this way, the resistance of a lower electrode 59 of a capacitance device can be lowered.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: April 6, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yasuhiro Sugawara, Ryouichi Furukawa, Toshio Uemura, Akira Takamatsu, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Shinpei Iljima, Yuzuru Ohji
  • Publication number: 20030148600
    Abstract: Conductive layers are formed in the trenches made in an insulating film in the following manner. First, an amorphous silicon film 26A is deposited in the trenches 25 made in a silicon oxide film 24. A photoresist film 30 is then formed on the amorphous silicon film 26A by means of spin coating. Then, exposure light is applied to the entire surface of the photoresist film 30, thereby exposing to light those parts of the photoresist film 30 which lie outside the trenches 25. The other parts of the photoresist film 30, which lie in the trenches 25 are not exposed to light because the light reaching them is inadequate. Further, the photoresist film 30 is developed thereby removing those parts of the film 30 which lie outside the trenches 25 and which have been exposed to light. Thereafter, those parts of the amorphous silicon film 26A, which lie outside the trenches 25, are removed by means of dry etching using, as a mask, the unexposed parts of the photoresist film 30 which remain in the trenches 25.
    Type: Application
    Filed: February 19, 2003
    Publication date: August 7, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Ryouichi Furukawa, Kazuyuki Suko, Masayuki Hiranuma, Koichi Saitoh, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Maki Shimoda
  • Patent number: 6576946
    Abstract: Capacitors are stretched over a plurality of memory cells in the direction of a bit line in order to effectively utilize spaces between adjacent cells. In addition, by creating a cubic structure of each capacitor by adoption of a self-matching technique, the structure can be utilized more effectively. As a result, it is possible to assure a sufficient capacitor capacitance in spite of a limitation imposed by the fabrication technology and obtain an assurance of sufficient space between cells in a shrunk area of a memory cell accompanying high-scale integration and miniaturization of a semiconductor device.
    Type: Grant
    Filed: July 20, 1999
    Date of Patent: June 10, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Misuzu Kanai, Yuzuru Ohji, Takuya Fukuda, Shinpei Iijima, Ryouichi Furukawa, Yasuhiro Sugawara, Hideharu Yahata
  • Publication number: 20030052353
    Abstract: A silicon oxide film on which a capacitor of a semiconductor integrated circuit device is formed is formed by the plasma CVD method at a temperature of 450° C. to 700° C. In this semiconductor integrated circuit device, a memory cell formed of a MISFET for data transfer and a capacitor is formed in a memory cell forming area, and an n channel MISFET and a p channel MISFET constituting a logic circuit is formed in a logic circuit forming area. As a result, the amount of degassing from the silicon oxide film can be reduced. Therefore, the growth of silicon grains on a surface of the silicon film constituting a lower electrode of the capacitor is not hindered by the degassing, and it becomes possible to increase the capacitance. Also, the step of a heat treatment for removing the moisture and the like after forming the silicon oxide film can be omitted, and it becomes possible to prevent the deterioration of the property of the MISFET.
    Type: Application
    Filed: February 27, 2002
    Publication date: March 20, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Tsuyoshi Fujiwara, Takeshi Saikawa, Ryouichi Furukawa, Masato Kunitomo
  • Publication number: 20030038325
    Abstract: A first silicon film is so formed as to extend along the inner surface of trenches 52 formed in a silicon oxide film 50, an oxide film is formed on the surface of the first silicon film, and a second amorphous silicon film is further deposited. Heat-treatment is applied to the surface of the second amorphous silicon film for seeding silicon nuclei and for promoting grain growth, and a granular silicon crystal 57 is grown from the second amorphous silicon film. In this way, the resistance of a lower electrode 59 of a capacitance device can be lowered.
    Type: Application
    Filed: October 17, 2002
    Publication date: February 27, 2003
    Inventors: Yasuhiro Sugawara, Ryouichi Furukawa, Toshio Uemura, Akira Takamatsu, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Shinpei Iijima, Yuzuru Ohji
  • Patent number: 6524927
    Abstract: A first silicon film is so formed as to extend along the inner surface of trenches 52 formed in a silicon oxide film 50, an oxide film is formed on the surface of the first silicon film, and a second amorphous silicon film is further deposited. Heat-treatment is applied to the surface of the second amorphous silicon film for seeding silicon nuclei and for promoting grain growth, and a granular silicon crystal 57 is grown from the second amorphous silicon film. In this way, the resistance of a lower electrode 59 of a capacitance device can be lowered.
    Type: Grant
    Filed: September 7, 1999
    Date of Patent: February 25, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yasuhiro Sugawara, Ryouichi Furukawa, Toshio Uemura, Akira Takamatsu, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Shinpei Iljima, Yuzuru Ohji
  • Patent number: 6444405
    Abstract: Conductive layers are formed in the trenches made in an insulating film in the following manner. First, an amorphous silicon film 26A is deposited in the trenches 25 made in a silicon oxide film 24. A photoresist film 30 is then formed on the amorphous silicon film 26A by means of spin coating. Then, exposure light is applied to the entire surface of the photoresist film 30, thereby exposing to light those parts of the photoresist film 30 which lie outside the trenches 25. The other parts of the photoresist film 30, which lie in the trenches 25 are not exposed to light because the light reaching them is inadequate. Further, the photoresist film 30 is developed thereby removing those parts of the film 30 which lie outside the trenches 25 and which have been exposed to light. Thereafter, those parts of the amorphous silicon film 26A, which lie outside the trenches 25, are removed by means of dry etching using, as a mask, the unexposed parts of the photoresist film 30 which remain in the trenches 25.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: September 3, 2002
    Assignees: Hitachi, Ltd., Hitachi Ulsi Systems Co., LTD
    Inventors: Ryouichi Furukawa, Kazuyuki Suko, Masayuki Hiranuma, Koichi Saitoh, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Maki Shimoda
  • Publication number: 20020098678
    Abstract: Conductive layers are formed in the trenches made in an insulating film in the following manner. First, an amorphous silicon film 26A is deposited in the trenches 25 made in a silicon oxide film 24. A photoresist film 30 is then formed on the amorphous silicon film 26A by means of spin coating. Then, exposure light is applied to the entire surface of the photoresist film 30, thereby exposing to light those parts of the photoresist film 30 which lie outside the trenches 25. The other parts of the photoresist film 30, which lie in the trenches 25 are not exposed to light because the light reaching them is inadequate. Further, the photoresist film 30 is developed thereby removing those parts of the film 30 which lie outside the trenches 25 and which have been exposed to light. Thereafter, those parts of the amorphous silicon film 26A, which lie outside the trenches 25, are removed by means of dry etching using, as a mask, the unexposed parts of the photoresist film 30 which remain in the trenches 25.
    Type: Application
    Filed: April 2, 2002
    Publication date: July 25, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Ryouichi Furukawa, Kazuyuki Suko, Masayuki Hiranuma, Koichi Saitoh, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Maki Shimoda