Patents by Inventor Ryouichi Kawano
Ryouichi Kawano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240097015Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity-type: an insulated gate electrode structure buried in a first trench provided in the semiconductor substrate; a base region of a second conductivity-type provided in the semiconductor substrate so as to be in contact with the first trench; a first main electrode region of the first conductivity-type provided at an upper part of the base region so as to be in contact with the first trench: a polysilicon film of the second conductivity-type having a higher impurity concentration than the base region and buried in a second trench provided in the semiconductor substrate so as to be in contact with the base region; and a second main electrode region provided on a bottom surface side of the semiconductor substrate.Type: ApplicationFiled: August 28, 2023Publication date: March 21, 2024Applicant: FUJI ELECTRIC CO., LTD.Inventors: Ryouichi KAWANO, Motoyoshi KUBOUCHI
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Patent number: 11081410Abstract: A method of manufacturing a semiconductor device from a semiconductor wafer in which a plurality of semiconductor chips are formed. The method includes a first process of forming an active region on a first main surface side of the semiconductor wafer and a second process of forming a first process control monitor (PCM) on a second main surface side of the semiconductor wafer. The method further includes before the second process, a third process of forming a second PCM on the first main surface side of the semiconductor wafer. The first PCM and the second PCM are formed at an area located at the same position in a plan view of the semiconductor wafer.Type: GrantFiled: August 27, 2019Date of Patent: August 3, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Hiroshi Takishita, Kazuhiro Kitahara, Ryouichi Kawano, Motoyoshi Kubouchi
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Patent number: 10896961Abstract: A semiconductor device is provided comprising an active portion and a terminating structure. The semiconductor device is provided comprising the active portion provided in the semiconductor substrate and a terminating structure provided at a termination of the front surface side of the semiconductor substrate and that mitigates an electric field of the termination. In the electric field distribution of the front surface side of the terminating structure, during rated voltage application, an electric field at the end portion of the active portion side may be smaller than a maximum value of an electric field distribution of the front surface side. In addition, the electric field distribution of the terminating structure may have a maximum peak of the electric field on the edge side opposite to the active portion with respect to a center of the terminating structure.Type: GrantFiled: December 21, 2018Date of Patent: January 19, 2021Inventors: Daisuke Ozaki, Ryouichi Kawano
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Publication number: 20200135593Abstract: A method of manufacturing a semiconductor device from a semiconductor wafer in which a plurality of semiconductor chips are formed. The method includes a first process of forming an active region on a first main surface side of the semiconductor wafer and a second process of forming a first process control monitor (PCM) on a second main surface side of the semiconductor wafer. The method further includes before the second process, a third process of forming a second PCM on the first main surface side of the semiconductor wafer. The first PCM and the second PCM are formed at an area located at the same position in a plan view of the semiconductor wafer.Type: ApplicationFiled: August 27, 2019Publication date: April 30, 2020Applicant: FUJI ELECTRIC CO., LTD.Inventors: Hiroshi TAKISHITA, Kazuhiro KITAHARA, Ryouichi KAWANO, Motoyoshi KUBOUCHI
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Publication number: 20190131412Abstract: A semiconductor device is provided comprising an active portion and a terminating structure. The semiconductor device is provided comprising the active portion provided in the semiconductor substrate and a terminating structure provided at a termination of the front surface side of the semiconductor substrate and that mitigates an electric field of the termination. In the electric field distribution of the front surface side of the terminating structure, during rated voltage application, an electric field at the end portion of the active portion side may be smaller than a maximum value of an electric field distribution of the front surface side. In addition, the electric field distribution of the terminating structure may have a maximum peak of the electric field on the edge side opposite to the active portion with respect to a center of the terminating structure.Type: ApplicationFiled: December 21, 2018Publication date: May 2, 2019Inventors: Daisuke OZAKI, Ryouichi KAWANO
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Patent number: 9450110Abstract: The semiconductor device includes a p-anode region disposed on an n-drift region, and a p-diffusion region disposed so as to be in contact with the p-anode region on the n-drift region. A resistance region disposed so as to be in contact with the p-diffusion region on an n? region, a plurality of p-guard ring regions, and a stopper region disposed away from the p-guard ring regions are provided. By providing the p-diffusion region, withdrawal of holes that concentrate to the p-anode region at the time of reverse recovery is suppressed, so that the semiconductor device has a high reverse recovery tolerance.Type: GrantFiled: August 7, 2015Date of Patent: September 20, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Ryouichi Kawano, Takashi Shiigi
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Publication number: 20150349144Abstract: The semiconductor device includes a p-anode region disposed on an n-drift region, and a p-diffusion region disposed so as to be in contact with the p-anode region on the n-drift region. A resistance region disposed so as to be in contact with the p-diffusion region on an n? region, a plurality of p-guard ring regions, and a stopper region disposed away from the p-guard ring regions are provided. By providing the p-diffusion region, withdrawal of holes that concentrate to the p-anode region at the time of reverse recovery is suppressed, so that the semiconductor device has a high reverse recovery tolerance.Type: ApplicationFiled: August 7, 2015Publication date: December 3, 2015Applicant: FUJI ELECTRIC CO., LTD.Inventors: Ryouichi KAWANO, Takashi SHIIGI
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Patent number: 8716826Abstract: In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region.Type: GrantFiled: April 16, 2012Date of Patent: May 6, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Ryouichi Kawano, Tomoyuki Yamazaki, Michio Nemoto, Mituhiro Kakefu
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Publication number: 20120193749Abstract: In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region.Type: ApplicationFiled: April 16, 2012Publication date: August 2, 2012Applicant: Fuji Electric Device Technology Co., Ltd.Inventors: Ryouichi KAWANO, Tomoyuki Yamazaki, Michio Nemoto, Mituhiro Kakefu
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Patent number: 8178941Abstract: In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region.Type: GrantFiled: July 22, 2009Date of Patent: May 15, 2012Assignee: Fuji Electric Co., Ltd.Inventors: Ryouichi Kawano, Tomoyuki Yamazaki, Michio Nemoto, Mituhiro Kakefu
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Publication number: 20100019342Abstract: In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region.Type: ApplicationFiled: July 22, 2009Publication date: January 28, 2010Applicant: Fuji Electric Device Technology Co., Ltd.Inventors: Ryouichi KAWANO, Tomoyuki YAMAZAKI, Michio NEMOTO, Mituhiro KAKEFU