Patents by Inventor Ryouichi Miyamoto

Ryouichi Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5631499
    Abstract: A semiconductor device having a bump electrode includes a first conductive layer formed on a predetermined portion of a substrate. An insulating layer is formed on the substrate and the first conductive layer. The insulating layer has an opening portion such that a predetermined portion of the first conductive layer is exposed. A second conductive layer is formed on the first conductive layer, a side wall of the opening portion of the insulating layer, and an upper surface of the insulating layer. A third conductive layer is formed to cover at least the insulating layer on the first conductive layer and the second conductive layer along the portion. A fourth conductive layer is formed on the third conductive layer to have an over hang portion. A side etch portion is formed surrounded with an over hang portion of the fourth conductive layer, the third conductive layer, and the insulating layer.
    Type: Grant
    Filed: June 3, 1996
    Date of Patent: May 20, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiichi Hosomi, Chiaki Takubo, Hiroshi Tazawa, Ryouichi Miyamoto, Takashi Arai, Koji Shibasaki
  • Patent number: 4874086
    Abstract: A film carrier for a semiconductor device tested with a tester having a plurality of test pins arranged with predetermined interval, comprises a film substrate of insulating material. A plurality of conductive leads are arranged on the film substrate with predetermined spacing with respect to an adjacent one. Each lead has testing lead portion and circuit lead portion. The spacing between the adjacent testing lead portion is larger than the spacing between the adjacent circuit lead portion. The testing lead portion is removed partially from the conductive lead after an efficiency test.
    Type: Grant
    Filed: May 20, 1988
    Date of Patent: October 17, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Imamura, Ryouichi Miyamoto