Patents by Inventor Ryouji Kosugi

Ryouji Kosugi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230282695
    Abstract: An active region includes a first super junction layer and an element layer. The first super junction layer alternately has a first region and a second region. A peripheral region includes a second super junction layer, a termination layer, and an insulating layer. The second super junction layer alternately has a third region and a fourth region. The termination layer is provided on and in contact with the second super junction layer, and alternately has a fifth region and a sixth region. The fifth region is provided to correspond to the third region, and the sixth region is provided to correspond to the fourth region. An impurity concentration of the sixth region is larger than an impurity concentration of the fifth region and is 68 times or less as large as the impurity concentration of the fifth region.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 7, 2023
    Inventors: Takeyoshi MASUDA, Ryouji KOSUGI
  • Publication number: 20230261042
    Abstract: A super junction layer alternately has a first region and a second region. An element layer is provided above the super junction layer. The first region has a first portion and a second portion located between the first portion and a first main surface. The second region has a third portion in contact with the first portion and a fourth portion in contact with the second portion and located between the third portion and the first main surface. In a cross section perpendicular to the second main surface and parallel to a direction from the first region toward the second region, a width of the second portion is larger than a width of the first portion, a width of the fourth portion is smaller than a width of the third portion.
    Type: Application
    Filed: May 26, 2021
    Publication date: August 17, 2023
    Inventors: Takeyoshi MASUDA, Ryouji KOSUGI
  • Patent number: 10756188
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate includes a first impurity region, a second impurity region, a third impurity region, a fourth impurity region, a fifth impurity region, and a sixth impurity region. A first main surface of the silicon carbide substrate is provided with a trench defined by a side surface and a bottom portion. The sixth impurity region includes a first region which faces the bottom portion and a second region which faces a second main surface of the silicon carbide substrate. The first region is higher in impurity concentration than the second region. In a direction perpendicular to the second main surface, a fifth main surface of the fourth impurity region is located between a sixth main surface of the second impurity region and the second main surface.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: August 25, 2020
    Assignees: Sumitomo Electric Industries, Ltd., National Institute of Advanced Industrial Science and Technology
    Inventors: Toru Hiyoshi, Takeyoshi Masuda, Ryouji Kosugi
  • Publication number: 20190074360
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate includes a first impurity region, a second impurity region, a third impurity region, a fourth impurity region, a fifth impurity region, and a sixth impurity region. A first main surface of the silicon carbide substrate is provided with a trench defined by a side surface and a bottom portion. The sixth impurity region includes a first region which faces the bottom portion and a second region which faces a second main surface of the silicon carbide substrate. The first region is higher in impurity concentration than the second region. In a direction perpendicular to the second main surface, a fifth main surface of the fourth impurity region is located between a sixth main surface of the second impurity region and the second main surface.
    Type: Application
    Filed: March 22, 2017
    Publication date: March 7, 2019
    Inventors: Toru Hiyoshi, Takeyoshi Masuda, Ryouji Kosugi
  • Patent number: 7265388
    Abstract: A semiconductor device formed on a silicon carbide semiconductor substrate comprises an epitaxial layer formed on a surface sloping (or inclining) by 0 to less than 1 degree from a (000-1) face of the silicon carbide semiconductor substrate, wherein at least one of a P type semiconductor area or an N type semiconductor area is selectively formed in the epitaxial layer by ion implantation, a metal electrode is formed so as to contact a surface layer of the P type semiconductor area or the N type semiconductor area, a rectification function is shown between the metal electrode and the P type semiconductor area or the N type semiconductor area, and the semiconductor device is formed on the silicon carbide semiconductor substrate of a Schottky barrier diode or a PN type diode.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: September 4, 2007
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Kenji Fukuda, Ryouji Kosugi, Shinsuke Harada, Junji Senzaki, Kazutoshi Kojima, Satoshi Kuroda
  • Publication number: 20050077591
    Abstract: A semiconductor device formed on a silicon carbide semiconductor substrate comprises an epitaxial layer formed on a surface sloping (or inclining) by 0 to less than 1 degree from a (000-1) face of the silicon carbide semiconductor substrate, wherein at least one of a P type semiconductor area or an N type semiconductor area is selectively formed in the epitaxial layer by ion implantation, a metal electrode is formed so as to contact a surface layer of the P type semiconductor area or the N type semiconductor area, a rectification function is shown between the metal electrode and the P type semiconductor area or the N type semiconductor area, and the semiconductor device is formed on the silicon carbide semiconductor substrate of a Schottky barrier diode or a PN type diode.
    Type: Application
    Filed: August 30, 2004
    Publication date: April 14, 2005
    Inventors: Kenji Fukuda, Ryouji Kosugi, Shinsuke Harada, Junji Senzaki, Kazutoshi Kojima, Satoshi Kuroda