Patents by Inventor Ryousei Kawai

Ryousei Kawai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9583783
    Abstract: A prismatic secondary battery includes: an electrode group including electrodes formed of positive electrodes and negative electrodes each having an active material layer coated on a surface of a metallic foil, the electrodes formed of positive and negative electrodes are flatly wound together with a separator intervening with the positive and negative electrodes, the positive and negative electrodes being each formed with a metallic foil exposed section at one end in a direction of a winding axis L; and connection plates that electrically connect the electrode group and electrode terminals. The metallic foil exposed sections of the electrode group and the connection plates are press-joined. At least a portion of the press-joined sections constituted by the metallic foil exposed sections and the connection plates is covered with a resin material.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: February 28, 2017
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Yuichi Takatsuka, Yoshio Onodera, Ryousei Kawai, Suguru Watashi
  • Publication number: 20150236369
    Abstract: A prismatic secondary battery includes: an electrode group including electrodes formed of positive electrodes and negative electrodes each having an active material layer coated on a surface of a metallic foil, the electrodes formed of positive and negative electrodes are flatly wound together with a separator intervening with the positive and negative electrodes, the positive and negative electrodes being each formed with a metallic foil exposed section at one end in a direction of a winding axis L; and connection plates that electrically connect the electrode group and electrode terminals. The metallic foil exposed sections of the electrode group and the connection plates are press-joined. At least a portion of the press-joined sections constituted by the metallic foil exposed sections and the connection plates is covered with a resin material.
    Type: Application
    Filed: June 26, 2013
    Publication date: August 20, 2015
    Applicant: Hitachi Automotive Systems, Ltd.
    Inventors: Yuichi Takatsuka, Yoshio Onodera, Ryousei Kawai, Suguru Watashi
  • Patent number: 7977234
    Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: July 12, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
  • Publication number: 20100227474
    Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
    Type: Application
    Filed: May 18, 2010
    Publication date: September 9, 2010
    Inventors: Toshiyuki ARAI, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
  • Patent number: 7718526
    Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: May 18, 2010
    Assignee: Renesas Technology Corporation
    Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
  • Publication number: 20070259522
    Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
    Type: Application
    Filed: July 16, 2007
    Publication date: November 8, 2007
    Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
  • Patent number: 7250365
    Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: July 31, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
  • Patent number: 6979649
    Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the water, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edges of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: December 27, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
  • Publication number: 20050250331
    Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
    Type: Application
    Filed: June 28, 2005
    Publication date: November 10, 2005
    Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
  • Patent number: 6723144
    Abstract: A film formed on a surface of a wafer on which an integrated circuit is to be constructed can be planarized by using a fixed abrasive tool regardless of the width of elements of a pattern underlying the film. The fixed abrasive tool is liable to form scratches in the surface of the film. A planarizing process of the present invention employs a fixed abrasive tool containing substances harder than the film to be planarized in a content of 10 ppm or below and having a mean pore diameter of 0.2 &mgr;m or below.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: April 20, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Souichi Katagiri, Kan Yasui, Ryousei Kawai, Sadayuki Nishimura, Masahiko Sato, Yoshio Kawamura, Shigeo Moriyama
  • Patent number: 6612912
    Abstract: A method for fabricating a semiconductor device includes grindstone surface activation treatment by means of a brush or ultrasonic wave carried out when a concave/convex pattern of a semiconductor wafer is planarized by polishing a semiconductor wafer held by a wafer holder by using a grindstone constituted of abrasive grains and material for holding the abrasive grains onto which the semiconductor wafer is pressed with relative motion. The semiconductor wafer is processed with high removal rate and the polishing thickness is controlled accurately.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: September 2, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kan Yasui, Souichi Katagiri, Shigeo Moriyama, Yoshio Kawamura, Ryousei Kawai, Sadayuki Nishimura, Masahiko Sato
  • Publication number: 20030084998
    Abstract: A film formed on a surface of a wafer on which an integrated circuit is to be constructed can be planarized by using a fixed abrasive tool regardless of the width of elements of a pattern underlying the film. The fixed abrasive tool is liable to form scratches in the surface of the film. A planarizing process of the present invention employs a fixed abrasive tool containing substances harder than the film to be planarized in a content of 10 ppm or below and having a mean pore diameter of 0.2 &mgr;m or below.
    Type: Application
    Filed: December 3, 2002
    Publication date: May 8, 2003
    Inventors: Souichi Katagiri, Kan Yasui, Ryousei Kawai, Sadayuki Nishimura, Masahiko Sato, Yoshio Kawamura, Shigeo Moriyama
  • Patent number: 6524961
    Abstract: A film formed on a surface of a wafer on which an integrated circuit is to be constructed can be planarized by using a fixed abrasive tool regardless of the width of elements of a pattern underlying the film. The fixed abrasive tool is liable to form scratches in the surface of the film. A planarizing process of the present invention employs a fixed abrasive tool containing substances harder than the film to be planarized in a content of 10 ppm or below and having a mean pore diameter of 0.2 &mgr;m or below.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: February 25, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Souichi Katagiri, Kan Yasui, Ryousei Kawai, Sadayuki Nishimura, Masahiko Sato, Yoshio Kawamura, Shigeo Moriyama
  • Publication number: 20020160610
    Abstract: A fabrication method of a semiconductor integrated circuit device including polishing the entire area of an edge of a wafer, for example, by using three polishing drums in which a polishing drum polishes the upper surface of the edge of the water relatively, the polishing drum polishes the central portion of the edge of the wafer relatively and a polishing drum polishes the lower surface of the edge of the wafer relatively, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.
    Type: Application
    Filed: March 1, 2002
    Publication date: October 31, 2002
    Inventors: Toshiyuki Arai, Ryousei Kawai, Hirofumi Tsuchiyama, Fumiyuki Kanai, Shinichi Nakabayashi
  • Publication number: 20020119733
    Abstract: A method for fabricating a semiconductor device includes grindstone surface activation treatment by means of a brush or ultrasonic wave carried out when a concave/convex pattern of a semiconductor wafer is planarized by polishing a semiconductor wafer held by a wafer holder by using a grindstone constituted of abrasive grains and material for holding the abrasive grains onto which the semiconductor wafer is pressed with relative motion. The semiconductor wafer is processed with high removal rate and the polishing thickness is controlled accurately.
    Type: Application
    Filed: August 10, 1999
    Publication date: August 29, 2002
    Inventors: KAN YASUI, SOUICHI KATAGIRI, SHIGEO MORIYAMA, YOSHIO KAWAMURA, RYOUSEI KAWAI, SADAYUKI NISHIMURA, MASAHIKO SATO