Patents by Inventor Ryouta Yamamoto

Ryouta Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11916531
    Abstract: An acoustic wave device includes a support substrate, a piezoelectric layer provided over the support substrate, comb-shaped electrodes disposed on the piezoelectric layer, each of the comb-shaped electrodes including electrode fingers exciting an acoustic wave, a temperature compensation film interposed between the support substrate and the piezoelectric layer and having a temperature coefficient of an elastic constant opposite in sign to that of the piezoelectric layer, a boundary layer interposed between the support substrate and the temperature compensation film, an acoustic velocity of a bulk wave propagating through the boundary layer being higher than an acoustic velocity of a bulk wave propagating through the temperature compensation film and being lower than an acoustic velocity of a bulk wave propagating through the support substrate, and an intermediate layer interposed between the support substrate and the boundary layer and having a Q factor less than a Q factor of the boundary layer.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: February 27, 2024
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Toshiharu Nakazato, Shinji Yamamoto, Ryouta Iwabuchi, Naoki Takahashi
  • Patent number: 11535777
    Abstract: To provide a double-sided pressure-sensitive adhesive sheet having high flexing resistance that does not suffer flexure and exfoliation in a flexing test that is closer to the actual use environment. A double-sided pressure-sensitive adhesive sheet having no substrate, containing a pressure-sensitive adhesive composition containing a (meth)acrylate ester (co)polymer (A), and having a glass transition temperature (Tg) defined by a Tan ? peak temperature of dynamic viscoelasticity in a range of ?50° C. to ?20° C., a storage elastic modulus G? at a frequency of 1 Hz and a temperature 100° C. in a range of 2.0×103 to 3.0×104 Pa, and a thickness of 10 ?m or more and 150 ?m or less.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: December 27, 2022
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Takahisa Uchida, Naoya Miara, Hidejirou Yoshikawa, Ryouta Yamamoto, Shinya Fukuda
  • Publication number: 20040089901
    Abstract: In a semiconductor integrated circuit, a P-type epitaxial layer is provided on the entire surface of a P-type bulk substrate. The resistivity of the P-type bulk substrate is set to 1000 &OHgr;·cm, and the thickness and the resistivity of the P-type epitaxial layer is set to 5 &mgr;m and 10 &OHgr;·cm, respectively. Then, a digital section and an analog section are provided remote from each other on the P-type epitaxial layer, where a digital circuit and an analog circuit are formed on the digital section and analog section, respectively. Further a device isolation region reaching the P-type bulk substrate is formed in a region between the digital section and analog section of the P-type epitaxial layer.
    Type: Application
    Filed: October 29, 2003
    Publication date: May 13, 2004
    Inventors: Hiroaki Ohkubo, Hiroaki Kikuchi, Masayuki Furumiya, Ryouta Yamamoto, Yasutaka Nakashiba