Patents by Inventor Ryu Kato

Ryu Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9192768
    Abstract: Implementation including a brain activity data acquisition unit configured to acquire data on brain activity of a human body; a generator configured to generate a stimulation signal based on predetermined stimulation parameters or stimulation parameters determined from the data acquired by the brain activity data acquisition unit, the stimulation signal being to be applied, for activity of a specific brain region to be activated in order to move a joint of the human body, to a nerve corresponding to the specific brain region; and an output unit configured to output the stimulation signal generated by the generator.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: November 24, 2015
    Assignees: The University of Electro-Communications, The University of Tokyo, National University Corporation University of Fukui
    Inventors: Hiroshi Yokoi, Ryu Kato, Tatsuhiro Nakamura, Soichiro Morishita, Osamu Yamamura
  • Patent number: 9111964
    Abstract: According one embodiment, a nonvolatile semiconductor memory device, includes: a stacked body, and each of a plurality of electrode layers and each of a plurality of insulating layers being stacked alternately in the a stacked body; a first interlayer insulating film on the stacked body; a gate electrode on the first interlayer insulating film; a second interlayer insulating film on the gate electrode; a semiconductor layer extended from an upper end of the second interlayer insulating film to a lower end of the stacked body; a first insulating film between the semiconductor layer and each of the plurality of electrode layers; and a second insulating film between the semiconductor layer and the gate electrode, a thickness of the semiconductor layer provided above an upper end of the gate electrode being thicker than a thickness of the semiconductor layer provided below the upper end of the gate electrode.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: August 18, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuru Sato, Soichiro Kitazaki, Ryu Kato, Masaru Kito, Ryota Katsumata
  • Publication number: 20140284693
    Abstract: According one embodiment, a nonvolatile semiconductor memory device, includes: a stacked body, and each of a plurality of electrode layers and each of a plurality of insulating layers being stacked alternately in the a stacked body; a first interlayer insulating film on the stacked body; a gate electrode on the first interlayer insulating film; a second interlayer insulating film on the gate electrode; a semiconductor layer extended from an upper end of the second interlayer insulating film to a lower end of the stacked body; a first insulating film between the semiconductor layer and each of the plurality of electrode layers; and a second insulating film between the semiconductor layer and the gate electrode, a thickness of the semiconductor layer provided above an upper end of the gate electrode being thicker than a thickness of the semiconductor layer provided below the upper end of the gate electrode.
    Type: Application
    Filed: September 6, 2013
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mitsuru SATO, Soichiro KITAZAKI, Ryu KATO, Masaru KITO, Ryota KATSUMATA
  • Publication number: 20140048862
    Abstract: A semiconductor device according to an embodiment, includes a first dielectric film, a floating gate, a second dielectric film, and a third dielectric film. The first dielectric film is formed above a semiconductor substrate. The floating gate is formed above the first dielectric film by using a silicon film. The third dielectric film is formed to cover an upper surface of the floating gate and a side face portion of the floating gate. The floating gate includes an impurity layer formed on an upper surface of the floating gate and a side face of the floating gate along an interface between the floating gate and the third dielectric film formed to cover the upper surface of the floating gate and a side face portion of the floating gate and containing at least one of carbon (C), nitrogen (N), and fluorine (F) as an impurity.
    Type: Application
    Filed: December 14, 2012
    Publication date: February 20, 2014
    Inventors: Junya Fujita, Fumiki Aiso, Ryu Kato
  • Publication number: 20130218238
    Abstract: Implementation including a brain activity data acquisition unit (103) configured to acquire data on brain activity of a human body; a generator (101) configured to generate a stimulation signal based on predetermined stimulation parameters or stimulation parameters determined from the data acquired by the brain activity data acquisition unit, the stimulation signal being to be applied, for activity of a specific brain region to be activated in order to move a joint of the human body, to a nerve corresponding to the specific brain region; and an output unit (102) configured to output the stimulation signal generated by the generator.
    Type: Application
    Filed: October 14, 2011
    Publication date: August 22, 2013
    Applicant: The University of Electro-Communications
    Inventors: Hiroshi Yokoi, Ryu Kato, Tatsuhiro Nakamura, Soichiro Morishita, Osamu Yamamura
  • Patent number: 8404537
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a conductive film whose upper surface and side surface are exposed and an insulation film whose upper surface is exposed, on a semiconductor substrate. The method further includes supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the exposed side surface of the conductive film and the exposed upper surface of the insulation film, by applying a predetermined voltage to the semiconductor substrate, thereby performing anisotropic oxidation or anisotropic nitridation of the exposed side surface of the conductive film and the exposed upper surface of the insulation film.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: March 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Isao Kamioka, Junichi Shiozawa, Ryu Kato, Yoshio Ozawa
  • Patent number: 8396546
    Abstract: A machine control device includes: first decoders for estimating, from brain signal information, which one of body movements a user performs or images, based on learning using pairs of movements performed by the user and brain signal information, the body movements going toward one of first to nth body postures; second decoders for estimating from the brain signal information, an correct rate on the body movement estimation, based on learning using pairs of correct rates of the estimation of body movements and the brain signal information; and electric prosthetic arm control section for controlling an electric prosthetic arm to change stepwise its posture between first to nth postures via at least one intermediate posture therebetween, the first to nth postures corresponding to the first to nth body postures. The first decoders perform the estimation only when the estimated correct rate exceeds a threshold.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: March 12, 2013
    Assignees: Osaka University, Advanced Telecommunications Research Institute International, The University of Tokyo
    Inventors: Masayuki Hirata, Takufumi Yanagisawa, Yukiyasu Kamitani, Hiroshi Yokoi, Toshiki Yoshimine, Tetsu Goto, Ryohei Fukuma, Ryu Kato
  • Publication number: 20120282773
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a conductive film whose upper surface and side surface are exposed and an insulation film whose upper surface is exposed, on a semiconductor substrate. The method further includes supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the exposed side surface of the conductive film and the exposed upper surface of the insulation film, by applying a predetermined voltage to the semiconductor substrate, thereby performing anisotropic oxidation or anisotropic nitridation of the exposed side surface of the conductive film and the exposed upper surface of the insulation film.
    Type: Application
    Filed: June 4, 2012
    Publication date: November 8, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Isao Kamioka, Junichi Shiozawa, Ryu Kato, Yoshio Ozawa
  • Publication number: 20120122294
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes successively forming first and second films to be processed on a semiconductor substrate. The method further includes removing a predetermined region of the second film by etching, to form a slit part including sidewall parts and a bottom part, the sidewall parts including side surfaces of the second film, and the bottom part including an upper surface of the first film. The method further includes supplying oxidizing ions or nitriding ions contained in plasma, generated by a microwave, a radio-frequency wave, or electron cyclotron resonance, to the sidewall parts and the bottom part of the slit part by applying a predetermined voltage to the semiconductor substrate, thereby performing anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the slit part.
    Type: Application
    Filed: December 15, 2011
    Publication date: May 17, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Isao Kamioka, Junichi Shiozawa, Ryu Kato, Yoshio Ozawa
  • Publication number: 20120034754
    Abstract: A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.
    Type: Application
    Filed: October 13, 2011
    Publication date: February 9, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuaki Iwasawa, Takeshi Hoshi, Keisuke Nakazawa, Shogo Matsuo, Takashi Nakao, Ryu Kato, Tetsuya Kai, Katsuyuki Sekine
  • Patent number: 8097503
    Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: January 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Isao Kamioka, Junichi Shiozawa, Ryu Kato, Yoshio Ozawa
  • Patent number: 8080463
    Abstract: A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: December 20, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuaki Iwasawa, Takeshi Hoshi, Keisuke Nakazawa, Shogo Matsuo, Takashi Nakao, Ryu Kato, Tetsuya Kai, Katsuyuki Sekine
  • Publication number: 20110218453
    Abstract: A machine control device includes: first decoders for estimating, from brain signal information, which one of body movements a user performs or images, based on learning using pairs of movements performed by the user and brain signal information, the body movements going toward one of first to nth body postures; second decoders for estimating from the brain signal information, an correct rate on the body movement estimation, based on learning using pairs of correct rates of the estimation of body movements and the brain signal information; and electric prosthetic arm control section for controlling an electric prosthetic arm to change stepwise its posture between first to nth postures via at least one intermediate posture therebetween, the first to nth postures corresponding to the first to nth body postures. The first decoders perform the estimation only when the estimated correct rate exceeds a threshold.
    Type: Application
    Filed: May 3, 2010
    Publication date: September 8, 2011
    Applicants: Osaka University, Advanced Telecommunications Research Institute International, The University of Tokyo
    Inventors: Masayuki Hirata, Takufumi Yanagisawa, Yukiyasu Kamitani, Hiroshi Yokoi, Toshiki Yoshimine, Tetsu Goto, Ryohei Fukuma, Ryu Kato
  • Publication number: 20110065262
    Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure.
    Type: Application
    Filed: November 12, 2010
    Publication date: March 17, 2011
    Inventors: Isao Kamioka, Junichi Shiozawa, Ryu Kato, Yoshio Ozawa
  • Patent number: 7858467
    Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: December 28, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Isao Kamioka, Junichi Shiozawa, Ryu Kato, Yoshio Ozawa
  • Publication number: 20100190317
    Abstract: A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.
    Type: Application
    Filed: January 21, 2010
    Publication date: July 29, 2010
    Inventors: Kazuaki IWASAWA, Takeshi Hoshi, Keisuke Nakazawa, Shogo Matsuo, Takashi Nakao, Ryu Kato, Tetsuya Kai, Katsuyuki Sekine
  • Publication number: 20090246932
    Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure.
    Type: Application
    Filed: March 27, 2009
    Publication date: October 1, 2009
    Inventors: Isao KAMIOKA, Junichi SHIOZAWA, Ryu KATO, Yoshio OZAWA