Patents by Inventor Ryu Takada

Ryu Takada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8489918
    Abstract: When a failure has occurred, the situation is dealt with promptly according to this invention. As triggered by detection of a failure in any specified processor package of a plurality of processor packages, a processor for the specified processor package is temporarily substituted with a processor for another processor package, as an assignment destination of ownership which is assigned to the processor for the specified processor package, instead of actually transferring the ownership, thereby making the transition to an ownership-substituted state; and as triggered by an event that the failure is no longer detected in the specified processor package, a processor for the other processor package cancels the ownership-substituted state.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: July 16, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Koji Watanabe, Ryu Takada, Kei Satoh, Yasuyuki Nagasoe
  • Patent number: 8285943
    Abstract: The storage control apparatus arranges, in microprocessor packages, management information relating to logical volumes managed by the microprocessor packages. In a predetermined case, each of the management information is rearranged in appropriate places. The management information can be moved, taking into account the difference in the technical properties between a mainframe and an open system host.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: October 9, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Ryu Takada, Yasuhiko Yamaguchi, Ran Ogata
  • Publication number: 20120117321
    Abstract: When a failure has occurred, the situation is dealt with promptly according to this invention. As triggered by detection of a failure in any specified processor package of a plurality of processor packages, a processor for the specified processor package is temporarily substituted with a processor for another processor package, as an assignment destination of ownership which is assigned to the processor for the specified processor package, instead of actually transferring the ownership, thereby making the transition to an ownership-substituted state; and as triggered by an event that the failure is no longer detected in the specified processor package, a processor for the other processor package cancels the ownership-substituted state.
    Type: Application
    Filed: April 21, 2010
    Publication date: May 10, 2012
    Applicant: HITACHI, LTD.
    Inventors: Koji Watanabe, Ryu Takada, Kei Satoh, Yasuyuki Nagasoe
  • Patent number: 7984245
    Abstract: Proposed is a storage system capable of preventing the compression of a cache memory caused by data remaining in a cache memory of a storage subsystem without being transferred to a storage area of an external storage, and maintaining favorable I/O processing performance of the storage subsystem. In this storage system where an external storage is connected to the storage subsystem and the storage subsystem provides a storage area of the external storage as its own storage area, provided is a volume for saving dirty data remaining in a cache memory of the storage subsystem without being transferred to the external volume. The storage system recognizes the compression of the cache memory, and eliminates the overload of the cache memory by saving dirty data in a save volume.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: July 19, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Ryu Takada, Yoshihito Nakagawa
  • Publication number: 20110167232
    Abstract: The storage control apparatus arranges, in microprocessor packages, management information relating to logical volumes managed by the microprocessor packages. In a predetermined case, each of the management information is rearranged in appropriate places.
    Type: Application
    Filed: June 18, 2009
    Publication date: July 7, 2011
    Applicant: HITACHI, LTD.
    Inventors: Ryu Takada, Yasuhiko Yamaguchi, Ran Ogata
  • Publication number: 20090307429
    Abstract: Proposed is a storage system capable of preventing the compression of a cache memory caused by data remaining in a cache memory of a storage subsystem without being transferred to a storage area of an external storage, and maintaining favorable I/O processing performance of the storage subsystem. In this storage system where an external storage is connected to the storage subsystem and the storage subsystem provides a storage area of the external storage as its own storage area, provided is a volume for saving dirty data remaining in a cache memory of the storage subsystem without being transferred to the external volume. The storage system recognizes the compression of the cache memory, and eliminates the overload of the cache memory by saving dirty data in a save volume.
    Type: Application
    Filed: August 15, 2008
    Publication date: December 10, 2009
    Inventors: Ryu Takada, Yoshihito Nakagawa
  • Publication number: 20080195832
    Abstract: A storage controller of the present invention writes data to a storage device, in which the storage unit is fixed, at a size that is larger than this storage unit, and curbs response performance degradation. A host sends write-data in a prescribed number of logical blocks in accordance with a basic I/O size defined at initialization. A controller respectively creates a guarantee code for each logical block, and appends same to the write-data. Write-data, to which a guarantee code has been appended, is stored in another prescribed number of logical blocks in accordance with a basic disk access size which is set at a value corresponding to the basic I/O size, and sent to a storage device. When an unused part is also stored in the storage device, the utilization efficiency of the storage area decreases, but the need to read out data located before and after data targeted for updating at data write is eliminated, thereby curbing the degradation of response performance.
    Type: Application
    Filed: January 7, 2008
    Publication date: August 14, 2008
    Inventors: Ryu Takada, Yoshihito Nakagawa, Shinichi Nakayama