Patents by Inventor Ryubi Okuda

Ryubi Okuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit device having clock buffers and method for arranging the clock buffers on the device
    Patent number: 7685552
    Abstract: This invention concerns a semiconductor integrated circuit device comprising a plurality of circuit elements arranged in a chip and operating in response to a same clock signal; clock buffers arranged at intersecting points decided based on positions of the plurality of circuit elements, the intersecting points being included in intersecting points of a pseudo mesh virtually assumed to cover up a region in the chip including the plurality of circuit elements; and a main wiring transmitting the clock signal to the clock buffers.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: March 23, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fujio Ishihara, Ryubi Okuda, Toshihiko Himeno, Hiroshige Fujii
  • SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF DESIGNING THEREOF
    Publication number: 20070240087
    Abstract: This invention concerns a semiconductor integrated circuit device comprising a plurality of circuit elements arranged in a chip and operating in response to a same clock signal; clock buffers arranged at intersecting points decided based on positions of the plurality of circuit elements, the intersecting points being included in intersecting points of a pseudo mesh virtually assumed to cover up a region in the chip including the plurality of circuit elements; and a main wiring transmitting the clock signal to the clock buffers.
    Type: Application
    Filed: March 26, 2007
    Publication date: October 11, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Fujio ISHIHARA, Ryubi Okuda, Toshihiko Himeno, Hiroshige Fujii
  • Driver circuit and system including driver circuit
    Patent number: 7113007
    Abstract: A driver circuit disclosed herein comprises a first inverter which comprises: a first transistor which is connected between a first power supply with a first voltage and a first output node; a second transistor which is connected between the first output node and a second power supply with a second voltage; and a voltage maintaining circuit which is provided between the second power supply and the second transistor and which maintains a voltage of the first output node in the vicinity of a threshold voltage of a transistor which is connected to the first output node even when the second transistor is turned on.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: September 26, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Natsuki Kushiyama, Ryubi Okuda
  • Driver circuit and system including driver circuit
    Publication number: 20050218941
    Abstract: A driver circuit disclosed herein comprises a first inverter which comprises: a first transistor which is connected between a first power supply with a first voltage and a first output node; a second transistor which is connected between the first output node and a second power supply with a second voltage; and a voltage maintaining circuit which is provided between the second power supply and the second transistor and which maintains a voltage of the first output node in the vicinity of a threshold voltage of a transistor which is connected to the first output node even when the second transistor is turned on.
    Type: Application
    Filed: October 15, 2004
    Publication date: October 6, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Natsuki Kushiyama, Ryubi Okuda