Abstract: An information processing apparatus includes a processor configured to acquire first information that indicates a correspondence relationship between a virtual identifier of a memory device and a first identifier of a slot to which the memory device is attached, acquire second information that indicates a correspondence relationship between a second identifier of a slot to which the memory device is attached and a state of the memory device, generate correspondence information that indicates a correspondence relationship among the virtual identifier, the first identifier, and the second identifier based on the first information and the second information, acquire, during an operation of the distributed storage, third information that indicates correspondence relationship between the virtual identifier and the first identifier and fourth information that indicates correspondence relationship between the second identifier and the state of the memory device, and update the correspondence information based on the

Abstract: An information processing apparatus includes a processor configured to acquire first information that indicates a correspondence relationship between a virtual identifier of a memory device and a first identifier of a slot to which the memory device is attached, acquire second information that indicates a correspondence relationship between a second identifier of a slot to which the memory device is attached and a state of the memory device, generate correspondence information that indicates a correspondence relationship among the virtual identifier, the first identifier, and the second identifier based on the first information and the second information, acquire, during an operation of the distributed storage, third information that indicates correspondence relationship between the virtual identifier and the first identifier and fourth information that indicates correspondence relationship between the second identifier and the state of the memory device, and update the correspondence information based on the

Abstract: A master-slave flip-flop circuit includes: a master circuit to receive input data in a first state of a reference clock and hold the input data in a second state of the reference clock to output intermediary data; and a slave circuit to receive the intermediary data in the second state and hold the intermediary data in the first state to output data, wherein the master circuit includes: a feedback two-input NOR gate to receive an output of the master circuit and a first clock; an input three-input NOR gate to receive the input data, a second clock, and a third clock; and a synthesis two-input NOR gate to receive an output of the input three-input NOR gate and an output of the feedback two-input NOR gate.

Abstract: A master-slave flip-flop circuit includes: a master circuit to receive input data in a first state of a reference clock and hold the input data in a second state of the reference clock to output intermediary data; and a slave circuit to receive the intermediary data in the second state and hold the intermediary data in the first state to output data, wherein the master circuit includes: a feedback two-input NOR gate to receive an output of the master circuit and a first clock; an input three-input NOR gate to receive the input data, a second clock, and a third clock; and a synthesis two-input NOR gate to receive an output of the input three-input NOR gate and an output of the feedback two-input NOR gate.

Abstract: A semiconductor memory device includes cells arranged in a matrix formation. Each of the cells includes a driver transistor, a read transistor which is controlled by a read word line and outputs read data read from the cell to a read bit line, a write transistor which is controlled by a write word line and supplies write data supplied from a write bit line to a cell capacitor connected to a gate of the driver transistor, and a column write select transistor which is controlled by a column write select signal line and is connected to the write transistor in series. The write data is supplied to the cell capacitor via both the column write select transistor and the write transistor.