Patents by Inventor Ryuichi Hashishita

Ryuichi Hashishita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit device having load means
    Patent number: 5185723
    Abstract: A semiconductor integrated circuit device comprises a first power source terminal, a second power source terminal, a wiring layer, a plurality of driving transistors, and load elements. The load elements are connected in parallel between the wiring layer and the first power source terminal and disposed at respective ends of the conductor. Transfer gate elements may be provided between the wiring layer and the load elements for separating the load elements from the driving elements.
    Type: Grant
    Filed: April 9, 1992
    Date of Patent: February 9, 1993
    Assignee: NEC Corporation
    Inventor: Ryuichi Hashishita
  • Wirings in semiconductor integrated circuit and method thereof
    Patent number: 4771329
    Abstract: In a semiconductor integrated circuit having a double-layered wiring construction, wirings between adjacent logic function blocks of the circuit are provided using first level wirings of the double-layered wiring construction, and wirings among logic function blocks or between two logic function blocks having at least one intervening logic function block are provided by second level wirings of the double-layered wiring construction.
    Type: Grant
    Filed: March 24, 1986
    Date of Patent: September 13, 1988
    Assignee: NEC Corporation
    Inventor: Ryuichi Hashishita
  • Semiconductor integrated circuit having complementary field effect transistors
    Patent number: 4716450
    Abstract: A semiconductor integrated circuit which can be fabricated at high-density and operate at a high speed. The integrated circuit is of the type having p-channel transistors formed on a first region and n-channel transistors formed on a second region adjacent to the first region. Power supply wirings and signal wirings are formed on the first and second regions in the same direction and in parallel.
    Type: Grant
    Filed: June 26, 1985
    Date of Patent: December 29, 1987
    Assignee: NEC Corporation
    Inventor: Ryuichi Hashishita