Abstract: In a content addressable memory (CAM), a spare CAM word serving as a redundant circuit is mounted in addition to a plurality of CAM words, and a storage section for holding information indicating whether there is a defective CAM word in the plurality of CAM words, and if there is one or more defective CAM word, address information of the defective CAM word. Control is applied according to the address information of the defective CAM word such that the defective CAM word is replaced with the spare CAM word. The search output of the defective CAM word is replaced with that of the spare CAM word. The spare CAM word serving as a redundant circuit is mounted without increasing a circuit scale and an output delay time, and a produce yield is improved.

Abstract: A content addressable memory having a function for extending a data width to a plurality of words includes an entry configuration set unit which sets the number of words to form one entry, and a logical-segment-to-physical-segment converting circuit for converting the logical segments in one entry to the physical segments according to the setting of the entry configuration. The content addressable memory further includes a word circuit chain having the maximum number of one-word circuits belonging to each physical block which are combined to form one entry. The one-word circuits have CAM words associated therewith, and are connected in series over the physical block. A group of the words at the same number in entries where one entry is composed of a plurality of words forms a logical segment.

Abstract: A content addressable memory (CAM) device according to the present invention is configured with binary CAM cells capable of holding binary data “0” and “1”, and is capable of being used either as a binary CAM device with the binary CAM cells being used as binary CAM cells or as a ternary CAM device with the binary CAM cells being used as ternary CAM cells capable of holding ternary data in a way in which, in each pair of two bits of the binary CAM cells, three states, “0,” “1,” and “X (don't care)” are assigned to four states, “00,” “01,” “10,” and “11,” expressed by two-bit data stored in the pair.

Abstract: A content addressable memory device includes a storage bit line pair for reading storage data from and writing storage data to a content addressable memory cell, a search bit line pair, wired independently from the storage bit line pair, for providing search data to the content addressable memory cell, and a first unit for realizing a smaller swing in the level of the search bit line pair by setting the potential of the search bit line pair to an intermediate potential between a power source potential and a ground potential during match searching, and/or a second unit for realizing a smaller swing in the level of a match line by setting a precharge level of the match line to the intermediate potential between the power source potential and the ground potential.

Abstract: A content addressable memory device includes a storage bit line pair for reading storage data from and writing storage data to a content addressable memory cell, a search bit line pair, wired independently from the storage bit line pair, for providing search data to the content addressable memory cell, and a first unit for realizing a smaller swing in the level of the search bit line pair by setting the potential of the search bit line pair to an intermediate potential between a power source potential and a ground potential during match searching, and/or a second unit for realizing a smaller swing in the level of a match line by setting a precharge level of the match line to the intermediate potential between the power source potential and the ground potential.

Abstract: An associative memory device in which a coincident output is held by each word and aging for word data can be efficiently performed such that the word data is made valid or invalid on the basis of the information. The associative memory device includes a plurality of words for storing data, for detecting the coincidence/non-coincidence between the data stored in the plurality of respective words and input search data. Each word further includes a memory for storing a coincidence line output by a searching operation, a storage memory for storing data representing whether the corresponding word is subjected to a searching operation or is available to write new data therein, a circuit for simultaneously setting/resetting the contents of the storage memory, and circuit for resetting/setting the memory for storing the coincidence line output by the storage memory.