Abstract: A data transmission method includes, detecting an incoming link training sequence that is transmitted from an upstream transmitter, generating a marker indicating a timing location of a word included in the incoming link training sequence, generating a self link training sequence based on a local reference clock, adjusting a time difference in the incoming link training sequence and the self link training sequence, and retransmitting an incoming bit stream based on the self link training sequence being matched to the incoming link training sequence.

Abstract: A data transmission method includes, detecting an incoming link training sequence that is transmitted from an upstream transmitter, generating a marker indicating a timing location of a word included in the incoming link training sequence, generating a self link training sequence based on a local reference clock, adjusting a time difference in the incoming link training sequence and the self link training sequence, and retransmitting an incoming bit stream based on the self link training sequence being matched to the incoming link training sequence.

Abstract: A transmitter cyclic pattern having a pattern length of N bits is generated and converted into an M-bit transmitter parallel data stream, where N?M. A bit-sequence altered transmitter parallel data stream is generated by performing a transmitter altering process, converted into a serial data and transmitted together with a clock signal. The serial data is received and converted into an M-bit receiver parallel data stream, and a bit-sequence restored parallel data stream is generated by performing a process opposite to the transmitter altering process. A receiver cyclic pattern is generated by using bits in the bit-sequence restored parallel data stream and converted into an M-bit reference parallel data stream, and a bit-sequence altered reference parallel data stream is generated by performing a process same as the transmitter altering process and compared with the received parallel data to test if the data is correctly received.

Abstract: A transmitter cyclic pattern having a pattern length of N bits is generated and converted into an M-bit transmitter parallel data stream, where N?M. A bit-sequence altered transmitter parallel data stream is generated by performing a transmitter altering process, converted into a serial data and transmitted together with a clock signal. The serial data is received and converted into an M-bit receiver parallel data stream, and a bit-sequence restored parallel data stream is generated by performing a process opposite to the transmitter altering process. A receiver cyclic pattern is generated by using bits in the bit-sequence restored parallel data stream and converted into an M-bit reference parallel data stream, and a bit-sequence altered reference parallel data stream is generated by performing a process same as the transmitter altering process and compared with the received parallel data to test if the data is correctly received.

Abstract: A transmitter cyclic pattern having a pattern length of N bits is generated and converted into an M-bit transmitter parallel data stream, where N?M. A bit-sequence altered transmitter parallel data stream is generated by performing a transmitter altering process, converted into a serial data and transmitted together with a clock signal. The serial data is received and converted into an M-bit receiver parallel data stream, and a bit-sequence restored parallel data stream is generated by performing a process opposite to the transmitter altering process. A receiver cyclic pattern is generated by using bits in the bit-sequence restored parallel data stream and converted into an M-bit reference parallel data stream, and a bit-sequence altered reference parallel data stream is generated by performing a process same as the transmitter altering process and compared with the received parallel data to test if the data is correctly received.

Abstract: A transmitter cyclic pattern having a pattern length of N bits is generated and converted into an M-bit transmitter parallel data stream, where N?M. A bit-sequence altered transmitter parallel data stream is generated by performing a transmitter altering process, converted into a serial data and transmitted together with a clock signal. The serial data is received and converted into an M-bit receiver parallel data stream, and a bit-sequence restored parallel data stream is generated by performing a process opposite to the transmitter altering process. A receiver cyclic pattern is generated by using bits in the bit-sequence restored parallel dada stream and converted into an M-bit reference parallel data stream, and a bit-sequence altered reference parallel data stream is generated by performing a process same as the transmitter altering process and compared with the received parallel data to test if the data is correctly received.

Abstract: A phase detector that compares the phases of data and four-phase first to fourth clocks having a half rate of the data and being 90° out of phase with one another. Exemplary embodiments of the phase detector include first to fourth sampling circuits that sample the data by the four-phase first to fourth clocks; a first comparator that compares sampling data obtained by sampling according to the adjacent two-phase first and second clocks using the first and second sampling circuits, respectively, and when the sampling data is different, outputs a first up signal; and a second comparator that compares sampling data obtained by sampling according to the adjacent two-phase fourth and first clocks using the fourth and first sampling circuits, respectively, and when the sampling data is different, outputs a first down signal.

Abstract: A phase detector that compares the phases of data and four-phase first to fourth clocks having a half rate of the data and being 90° out of phase with one another. Exemplary embodiments of the phase detector include first to fourth sampling circuits that sample the data by the four-phase first to fourth clocks; a first comparator that compares sampling data obtained by sampling according to the adjacent two-phase first and second clocks using the first and second sampling circuits, respectively, and when the sampling data is different, outputs a first up signal; and a second comparator that compares sampling data obtained by sampling according to the adjacent two-phase fourth and first clocks using the fourth and first sampling circuits, respectively, and when the sampling data is different, outputs a first down signal.