Abstract: In an information processing apparatus, a control unit receives operation instructions. Each time receiving an operation instruction, the control unit detects the number of operating circuits that are to operate in accordance with the received operation instruction, in a circuit group of circuits that operate in synchronization with a clock signal. In addition, each time receiving an operation instruction, the control unit determines whether power supply noise that is likely to cause a timing error in the circuit group will occur, on the basis of a result of comparing an increase in the number of operating circuits per prescribed time period with a threshold, and lowers the frequency of the clock signal when determining that the power supply noise will occur.

Abstract: A semiconductor device includes a power supply; and a plurality of processor cores configured to operate with the power supply, wherein each of the plurality of processor cores includes a clock control circuit that decreases an own clock frequency used by an own processor core when detecting drop of a power supply voltage of the own processor core, and adjusts a speed at which the own clock frequency is increased according to a situation of a power supply voltage of another processor core among the plurality of processor cores.

Abstract: An arithmetic processing device includes a plurality of arithmetic processing circuitry, each of which includes: an instruction hold circuit configured to hold an arithmetic instruction; an arithmetic circuit configured to execute an arithmetic instruction issued from the instruction hold circuit; and a measurement circuit configured to measure a predetermined time period, wherein the instruction hold circuit is configured to perform first processing after the instruction hold circuit holds a first arithmetic instruction when the arithmetic circuit is not executing other arithmetic instructions, the first processing being configured to: cause the measurement circuit to initiate the measurement of the predetermined time; and issue, in response to a completion of the measurement of the predetermined time period, the held first arithmetic instruction to the arithmetic circuit, and wherein the predetermined time period measured by the measurement circuit is different between at least two of the plurality of arith

Abstract: A semiconductor device includes a power supply; and a plurality of processor cores configured to operate with the power supply, wherein each of the plurality of processor cores includes a clock control circuit that decreases an own clock frequency used by an own processor core when detecting drop of a power supply voltage of the own processor core, and adjusts a speed at which the own clock frequency is increased according to a situation of a power supply voltage of another processor core among the plurality of processor cores.

Abstract: An arithmetic processing device includes a plurality of arithmetic processing circuitry, each of which includes: an instruction hold circuit configured to hold an arithmetic instruction; an arithmetic circuit configured to execute an arithmetic instruction issued from the instruction hold circuit; and a measurement circuit configured to measure a predetermined time period, wherein the instruction hold circuit is configured to perform first processing after the instruction hold circuit holds a first arithmetic instruction when the arithmetic circuit is not executing other arithmetic instructions, the first processing being configured to: cause the measurement circuit to initiate the measurement of the predetermined time; and issue, in response to a completion of the measurement of the predetermined time period, the held first arithmetic instruction to the arithmetic circuit, and wherein the predetermined time period measured by the measurement circuit is differ between at least two of the plurality of arithmet

Abstract: A noise detection circuit includes a first delay circuit which has a propagation delay of a first delay time when a signal propagates therethrough and a second delay circuit which has a propagation delay of a second delay time when the signal propagates therethrough, and outputs, based on a sum of the first delay time and the second delay time, a detection result indicating the magnitude of noise on power supply voltage applied to the first delay circuit and the second delay circuit. A control unit controls, based on the detection result, a frequency of a clock signal supplied to a circuit unit to which the power supply voltage is applied and the second delay time in such a manner as to exhibit an opposite behavior to a change in the first delay time induced by temperature.

Abstract: A noise detection circuit includes a first delay circuit which has a propagation delay of a first delay time when a signal propagates therethrough and a second delay circuit which has a propagation delay of a second delay time when the signal propagates therethrough, and outputs, based on a sum of the first delay time and the second delay time, a detection result indicating the magnitude of noise on power supply voltage applied to the first delay circuit and the second delay circuit. A control unit controls, based on the detection result, a frequency of a clock signal supplied to a circuit unit to which the power supply voltage is applied and the second delay time in such a manner as to exhibit an opposite behavior to a change in the first delay time induced by temperature.

Abstract: In an information processing apparatus, a control unit receives operation instructions. Each time receiving an operation instruction, the control unit detects the number of operating circuits that are to operate in accordance with the received operation instruction, in a circuit group of circuits that operate in synchronization with a clock signal. In addition, each time receiving an operation instruction, the control unit determines whether power supply noise that is likely to cause a timing error in the circuit group will occur, on the basis of a result of comparing an increase in the number of operating circuits per prescribed time period with a threshold, and lowers the frequency of the clock signal when determining that the power supply noise will occur.

Abstract: A communication circuit includes: a plurality of receiving units each configured to receive a serial signal over a transmission path from another device; a plurality of serial-to-parallel converters each configured to convert the received serial signal into a parallel signal; and a clock phase controller configured to send a clock phase control signal to any of the plurality of serial-to-parallel converters, wherein one of the serial-to-parallel converters that has received the clock phase control signal is configured to shift a phase of a parallel-signal clock signal that is to be used for a parallel signal obtained by conversion, so that a phase of a parallel signal to be obtained by conversion performed by the one of the serial-to-parallel converters is different from a phase of a parallel signal to be obtained by conversion performed by another one of the serial-to-parallel converters.

Abstract: A transmission/reception device includes a transmission circuit configured to apply a delay to at least one of a positive signal and a negative signal of differential signals to be sent to another device, detect a direction of a differential signal skew between the positive signal and the negative signal, to at least one of which the delay is applied, and control the delay in a manner as to reduce the differential signal skew; and a reception circuit configured to apply a delay to at least one of a positive signal and a negative signal of differential signals sent from another transmission/reception device, detect a direction of a differential signal skew between the positive signal and the negative signal, to at least one of which the delay is applied, and control the delay in a manner as to reduce the differential signal skew.

Abstract: A transmission/reception device includes a transmission circuit configured to apply a delay to at least one of a positive signal and a negative signal of differential signals to be sent to another device, detect a direction of a differential signal skew between the positive signal and the negative signal, to at least one of which the delay is applied, and control the delay in a manner as to reduce the differential signal skew; and a reception circuit configured to apply a delay to at least one of a positive signal and a negative signal of differential signals sent from another transmission/reception device, detect a direction of a differential signal skew between the positive signal and the negative signal, to at least one of which the delay is applied, and control the delay in a manner as to reduce the differential signal skew.

Abstract: A third periodic signal is synthesized using a first output signal having a phase corresponding to a first periodic signal and a second output signal having a phase corresponding to the second periodic signal. A value of the third periodic signal is detected at a timing of the phase of the delayed first periodic signal. The value of the third periodic signal detected with the delayed first periodic signal is compared with the value of the third periodic signal detected by the first periodic signal delayed by the different delay amount. The delay amount is obtained for the detected third periodic signal being a maximum or a minimum. In a state of the optimum delay amount, an amplitude of the third periodic signal is adjusted so that the detected value of the third periodic signal falls within a predetermined range.

Abstract: A variable delay circuit includes: a first delay section that changes a first drive capability or a first capacity load, receives the reference signals, and generates a first delayed signal by giving a first delay to the reference signal; a second delay section that changes a second drive capability or a second capacity load of the second delay section, receives the reference signal, and generates a second delayed signal by giving a second delay to the reference signal; a first capacity load setting section that sets at least one of the first capacity load and the second capacity load; a first phase comparing section that compares a first phase of the first delayed signal with a second phase of the second delayed signal; and a drive capability setting section that controls the first drive capability and the second drive capability.

Abstract: A variable delay circuit includes: a first delay section that changes a first drive capability or a first capacity load, receives the reference signals, and generates a first delayed signal by giving a first delay to the reference signal; a second delay section that changes a second drive capability or a second capacity load of the second delay section, receives the reference signal, and generates a second delayed signal by giving a second delay to the reference signal; a first capacity load setting section that sets at least one of the first capacity load and the second capacity load; a first phase comparing section that compares a first phase of the first delayed signal with a second phase of the second delayed signal; and a drive capability setting section that controls the first drive capability and the second drive capability.