Abstract: A piezoelectric thin film resonator includes: a substrate; a piezoelectric film located on the substrate; a lower electrode and an upper electrode facing each other across at least a part of the piezoelectric film; and a wiring layer located on the upper electrode, the wiring layer having a thickness equal to or greater than 0.8 ?m and equal to or less than 3.0 ?m, at least a part of the wiring layer overlapping in plan view with a resonance region in which the lower electrode and the upper electrode face each other across the piezoelectric film, a distance between an outline of the resonance region and an edge of a lower surface located within the resonance region and farthest from the outline being greater than 0 ?m and less than 2 ?m.

Abstract: A piezoelectric thin film resonator includes: a substrate; a piezoelectric film located on the substrate; a lower electrode and an upper electrode facing each other across at least a part of the piezoelectric film; and a wiring layer located on the upper electrode, the wiring layer having a thickness equal to or greater than 0.8 ?m and equal to or less than 3.0 ?m, at least a part of the wiring layer overlapping in plan view with a resonance region in which the lower electrode and the upper electrode face each other across the piezoelectric film, a distance between an outline of the resonance region and an edge of a lower surface located within the resonance region and farthest from the outline being greater than 0 ?m and less than 2 ?m.

Abstract: A piezoelectric thin film resonator includes: a lower electrode and an upper electrode facing each other across a piezoelectric film; an insertion film inserted into the piezoelectric film, located in at least a part of an outer peripheral region in a resonance region and outside the outer peripheral region, and not located in a center region of the resonance region; a protective film on the upper electrode and the piezoelectric film; and a wiring line connecting to the lower electrode and covering an outer periphery of the protective film in an extraction region of the lower electrode, wherein in the extraction region, an outer periphery of the insertion film is further out than an outer periphery of the upper electrode and further in than an outer periphery of the piezoelectric film, and the outer periphery of the protective film is further out than the outer periphery of the insertion film.

Abstract: A piezoelectric thin film resonator includes: a lower electrode and an upper electrode facing each other across a piezoelectric film; an insertion film inserted into the piezoelectric film, located in at least a part of an outer peripheral region in a resonance region and outside the outer peripheral region, and not located in a center region of the resonance region; a protective film on the upper electrode and the piezoelectric film; and a wiring line connecting to the lower electrode and covering an outer periphery of the protective film in an extraction region of the lower electrode, wherein in the extraction region, an outer periphery of the insertion film is further out than an outer periphery of the upper electrode and further in than an outer periphery of the piezoelectric film, and the outer periphery of the protective film is further out than the outer periphery of the insertion film.

Abstract: A semiconductor device, which exhibits an increased design flexibility for a capacitor element, and can be manufactured with simple method, is provided. A semiconductor device 100 includes: a silicon substrate 101; an interlayer film 103 provided on the silicon substrate 101; a multiple-layered interconnect embedded in the interlayer film 103; a flip-chip pad 111, provided so as to be opposite to an upper surface of an uppermost layer interconnect 105 in the multiple-layered interconnect and having a solder ball 113 for an external coupling mounted thereon; and a capacitance film 109 provided between said uppermost layer interconnect 105 and the flip-chip pad 111. Such semiconductor device 100 includes the flip-chip pad 111 composed of an uppermost layer interconnect 105, a capacitive film 109 and a capacitor element 110.

Abstract: In addition to a memory macro region and functional circuit regions on a substrate, a semiconductor integrated circuit device includes a dummy pattern region 40 arranged between the functional circuit regions and between the memory macro region 10 and the functional circuit regions and including a dummy pattern. The dummy pattern has a pattern identical to that of diffusion layers and gate electrodes of a memory cell pattern in a memory cell array region. An area ratio of dummy diffusion layer(s) and dummy gate electrode(s) in the dummy pattern region is equal to or greater than that of the diffusion layers and the gate electrode(s) in the memory cell array region.

Abstract: A semiconductor device, which exhibits an increased design flexibility for a capacitor element, and can be manufactured with simple method, is provided. A semiconductor device 100 includes: a silicon substrate 101; an interlayer film 103 provided on the silicon substrate 101; a multiple-layered interconnect embedded in the interlayer film 103; a flip-chip pad 111, provided so as to be opposite to an upper surface of an uppermost layer interconnect 105 in the multiple-layered interconnect and having a solder ball 113 for an external coupling mounted thereon; and a capacitance film 109 provided between said uppermost layer interconnect 105 and the flip-chip pad 111. Such semiconductor device 100 includes the flip-chip pad 111 composed of an uppermost layer interconnect 105, a capacitive film 109 and a capacitor element 110.

Abstract: A semiconductor device, which exhibits an increased design flexibility for a capacitor element, and can be manufactured with simple method, is provided. A semiconductor device 100 includes: a silicon substrate 101; an interlayer film 103 provided on the silicon substrate 101; a multiple-layered interconnect embedded in the interlayer film 103; a flip-chip pad 111, provided so as to be opposite to an upper surface of an uppermost layer interconnect 105 in the multiple-layered interconnect and having a solder ball 113 for an external coupling mounted thereon; and a capacitance film 109 provided between said uppermost layer interconnect 105 and the flip-chip pad 111. Such semiconductor device 100 includes the flip-chip pad 111 composed of an uppermost layer interconnect 105, a capacitive film 109 and a capacitor element 110.

Abstract: In addition to a memory macro region and functional circuit regions on a substrate, a semiconductor integrated circuit device includes a dummy pattern region 40 arranged between the functional circuit regions and between the memory macro region 10 and the functional circuit regions and including a dummy pattern. The dummy pattern has a pattern identical to that of diffusion layers and gate electrodes of a memory cell pattern in a memory cell array region. An area ratio of dummy diffusion layer(s) and dummy gate electrode(s) in the dummy pattern region is equal to or greater than that of the diffusion layers and the gate electrode(s) in the memory cell array region.

Abstract: The semiconductor device includes a semiconductor substrate, a diffusion layer, an interconnect layer, a contact plug, a contact-inspection hole, a via plug, and a via-inspection hole. Similarly to a contact plug hole, the contact-inspection hole extends from the diffusion layer to the interconnect layer. The opening of the contact-inspection hole on the side of the diffusion layer is disposed across the boundary of the diffusion layer. Also, similarly to a via plug hole, the via-inspection hole extends from an interconnect to an interconnect layer. The opening of the via-inspection hole on the side of the interconnect is disposed across the boundary of the interconnect.

Abstract: A length measurement pattern is used for forming a contact and a via on a diffusion layer and on a lower layer interconnect, respectively, with a photoresist. The length measurement pattern includes a first pattern 16 serving as an object of length measurement in length measurement SEM and a second pattern 17 disposed to be spaced apart from the first pattern 16 and used for positioning and focusing of the length measurement SEM.

Abstract: A semiconductor device, which exhibits an increased design flexibility for a capacitor element, and can be manufactured with simple method, is provided. A semiconductor device 100 includes: a silicon substrate 101; an interlayer film 103 provided on the silicon substrate 101; a multiple-layered interconnect embedded in the interlayer film 103; a flip-chip pad 111, provided so as to be opposite to an upper surface of an uppermost layer interconnect 105 in the multiple-layered interconnect and having a solder ball 113 for an external coupling mounted thereon; and a capacitance film 109 provided between said uppermost layer interconnect 105 and the flip-chip pad 111. Such semiconductor device 100 includes the flip-chip pad 111 composed of an uppermost layer interconnect 105, a capacitive film 109 and a capacitor element 110.

Abstract: A length measurement pattern is used for forming a contact and a via on a diffusion layer and on a lower layer interconnect, respectively, with a photoresist. The length measurement pattern includes a first pattern 16 serving as an object of length measurement in length measurement SEM and a second pattern 17 disposed to be spaced apart from the first pattern 16 and used for positioning and focusing of the length measurement SEM.

Abstract: The semiconductor device includes a semiconductor substrate, a diffusion layer, an interconnect layer, a contact plug, a contact-inspection hole, a via plug, and a via-inspection hole. Similarly to a contact plug hole, the contact-inspection hole extends from the diffusion layer to the interconnect layer. The opening of the contact-inspection hole on the side of the diffusion layer is disposed across the boundary of the diffusion layer. Also, similarly to a via plug hole, the via-inspection hole extends from an interconnect to an interconnect layer. The opening of the via-inspection hole on the side of the interconnect is disposed across the boundary of the interconnect.

Abstract: An apparatus for simulating a ride on a vehicle has a base, and a simulated vehicle body which is supported on the base with a freedom of two-axis rotation about a rolling axis and a pitching axis. A pair of linear actuators are disposed in a position offset to one side in an axial direction of one of the rolling axis and the pitching axis, e.g., offset to one axial side of the rolling axis relative to the pitching axis. The actuators are disposed symmetrically relative to a plane which crosses the pitching axis at a right angle and which includes an axial line of the rolling axis. A fixing member and a movable member of each of the actuators are coupled to the base and the simulated vehicle body, respectively, through universal joints.

Abstract: A semiconductor device includes a semiconductor substrate, a wiring formed on the semiconductor substrate, a cover film formed on the semiconductor substrate and the wiring. The cover film has a through hole to expose the wiring. A pad is formed in the through hole to electrically connect to the wiring without being formed on a top surface of the cover film.

Abstract: A semiconductor chip is mounted on a printed wiring board (PWB), with the pads of the semiconductor chip mounted on the electrodes of the PWB for flip-chip bonding. The density of the pads in the peripheral area is higher or lower compared to the density of the pads in the central area depending on the thermal shrinkage factor of the PWB being higher or lower compared to the thermal shrinkage factor of the semiconductor chip.

Abstract: A semiconductor device has at least a p-channel MOS field effect transistor and at least an n-channel MOS field effect transistor, both of which are integrated on a single semiconductor substrate. The p-channel MOS field effect transistor has at least a first p-type lightly doped diffusion region adjacent to a p-type drain diffusion region. The n-channel MOS field effect transistor has at least a first n-type lightly doped diffusion region adjacent to an n-type drain diffusion region. The first p-type lightly doped diffusion region of the p-channel MOS field effect transistor is shorter in a direction parallel to a channel length direction than a first n-type lightly doped diffusion region of the n-channel MOS field effect transistor.

Abstract: The invention provides a diffusion region structure in a semiconductor device wherein the diffusion region is applied with alternating voltages in an operation of the semiconductor device. The structure comprises at least one diffusion region being doped with an impurity of a first conductivity type at a first impurity concentration and also being provided in a semiconductor bulk region doped with an impurity of a second conductivity type at a second impurity concentration lower than the first impurity concentration, and at least a diffusion capacitance reduction layer provided under the diffusion region so as to be in contact with a bottom of the diffusion region.

Abstract: By assuming a symbol A for the contact depth, B for the diameter of the contact, C for the thickness of the underlay oxide to be formed between the barrier film and the semiconductor substrate, and D for the eave protrusion length of the barrier film the eaves being formed inside the contact when oxide wet etching is performed for removing natural oxide on the silicon and for reducing the contact resistance, the following relation is established,tan.sup.-1 (B/A)<tan.sup.-1 ((B-D)/(A-C)).A barrier film for checking penetration of the moisture from the outside may be composed of a nitride film, or the barrier film for checking penetration of the moisture from the outside may be composed of a film formed through nitrogen ion implanting applied on the surface of the underlay oxide.