Abstract: An optical receiver circuit is configured as follows: a preamplifier and a reference voltage generating circuit are connected with a first ground potential wiring and a first power supply wiring, which are used in common, and are formed in a first region where elements are formed on a substrate to which the potential of the first ground potential wiring is supplied; a main amplifier is connected with a second ground potential wiring and a second power supply wiring, which are separated from the first ground potential wiring and the first power supply wiring, and is formed in a second region where elements are formed on the substrate to which the potential of the second ground potential wiring is supplied; and a substrate supply interval where a first substrate supply position at which the potential of the first ground potential wiring is supplied and a second substrate supply position at which the potential of the second ground potential wiring is supplied are closest to each other is large to an extent where

Abstract: To solve problematic trade-off between a bandwidth and a in-band deviation in an optical signal receiving circuit of a gigabit order that is required to have a wide dynamic range, the optical signal receiving circuit has a current-voltage conversion circuit that receives as an input a current signal outputted from a photoelectric conversion circuit for receiving and converting an optical signal into a current signal and converts it into a voltage signal, and realizes the wide dynamic range by providing the current-voltage conversion circuit with an AGC function and a phase compensation function by MOS transistors and a capacitance. Further, by providing the current-voltage conversion circuit with a second phase compensation function by a MOS transistor and a capacitance, it is made possible for the optical signal receiving circuit to reduce the in-band deviation at the time of minimum gain while securing the bandwidth at the time of maximum gain.

Abstract: An optical receiver circuit is configured as follows: a preamplifier and a reference voltage generating circuit are connected with a first ground potential wiring and a first power supply wiring, which are used in common, and are formed in a first region where elements are formed on a substrate to which the potential of the first ground potential wiring is supplied; a main amplifier is connected with a second ground potential wiring and a second power supply wiring, which are separated from the first ground potential wiring and the first power supply wiring, and is formed in a second region where elements are formed on the substrate to which the potential of the second ground potential wiring is supplied; and a substrate supply interval where a first substrate supply position at which the potential of the first ground potential wiring is supplied and a second substrate supply position at which the potential of the second ground potential wiring is supplied are closest to each other is large to an extent where

Abstract: To solve problematic trade-off between a bandwidth and a in-band deviation in an optical signal receiving circuit of a gigabit order that is required to have a wide dynamic range, the optical signal receiving circuit has a current-voltage conversion circuit that receives as an input a current signal outputted from a photoelectric conversion circuit for receiving and converting an optical signal into a current signal and converts it into a voltage signal, and realizes the wide dynamic range by providing the current-voltage conversion circuit with an AGC function and a phase compensation function by MOS transistors and a capacitance. Further, by providing the current-voltage conversion circuit with a second phase compensation function by a MOS transistor and a capacitance, it is made possible for the optical signal receiving circuit to reduce the in-band deviation at the time of minimum gain while securing the bandwidth at the time of maximum gain.

Abstract: A programmable two-line, two-phase logic array has a plurality of inputs, each having two input signals operating in two phases and memory cells provided at an intersection of the input signal lines and output lines corresponding to at least one function that cross the input lines. The memory cells are capable of being written in the fabrication process or by a field programming process that addresses the contact points at which the input and output lines cross. The two-line, two-phase logic circuit can be attained by the same technique as that used for attaining a conventional PLA without designing circuitry based on a conventional synchronous logic beforehand followed by replacing it with a two-line, two-phase circuit.

Abstract: A second barrel shifter whose shift amount is equally controlled as that of a first barrel shifter for shifting input data by an optional bit is employed as a mask data generating circuit in a bit field operational arithmetic unit. Areas with transistor trains of the first and second barrel shifters are formed in parallel to an area having the same width as that of a 1-bit storage cell of a register file and shift amount control lines in both barrel shifters are set for common use so as to reduce the area occupied by a chip. In order to increase the processing speed of extracting an optional area of data, the bit field operational arithmetic unit is provided with a circuit for subjecting all bits to signal expansion in No. 0 bit data in parallel to the shift of input data effected by the first barrel shifter. Moreover, barrel shift circuits include left and right shift circuits as n shift circuits for shifting 2.sup.i -bit (i=0, 1, 2, . . . , n-1) data, with n as a positive integer.