Abstract: An arithmetic processing apparatus includes: first and second core groups each including cores, a first to an Nth (N is plural) caches that process access requests from the cores, and an intra-core-group bus through which the access requests from the cores are provided to the first to Nth caches; and a first to an Nth inter-core-group buses each provided between the first to Nth caches in the first and second core groups respectively. The first to Nth caches in the first core group individually store data from a first to an Nth memory spaces in a memory, respectively. The first to Nth caches in the second core group individually store data from an N+1th to a 2Nth memory spaces, respectively. The first to Nth caches in the first core group access the data in the N+1th to 2Nth memory spaces, respectively, via the first to Nth inter-core-group buses.

Abstract: An arithmetic processing apparatus includes: first and second core groups each including cores, a first to an Nth (N is plural) caches that process access requests from the cores, and an intra-core-group bus through which the access requests from the cores are provided to the first to Nth caches; and a first to an Nth inter-core-group buses each provided between the first to Nth caches in the first and second core groups respectively. The first to Nth caches in the first core group individually store data from a first to an Nth memory spaces in a memory, respectively. The first to Nth caches in the second core group individually store data from an N+1th to a 2Nth memory spaces, respectively. The first to Nth caches in the first core group access the data in the N+1th to 2Nth memory spaces, respectively, via the first to Nth inter-core-group buses.

Abstract: A processor including a circuit unit includes a state information holding unit, a direction controller, a direction generator, and a direction execution unit. The state information holding unit holds state information indicating a state of the circuit unit. The direction controller decodes a first direction for generating a control direction that is contained in a program. The direction generator generates a second direction when the first direction decoded by the direction controller is a direction for generating the second direction for reading the state information from the state information holding unit. The direction execution unit reads the state information from the state information holding unit based on the second direction generated by the direction generator so as to store the state information in a register unit that is capable of being read from a program.

Abstract: A processor including: a first storage unit that stores data; an error detection unit that detects an occurrence of error in data read out from the first storage unit; a second storage unit that stores data read out from the first storage unit based on a load request; a rerun request generation unit that generates a rerun request of a load request to the first storage unit in the same cycle as the cycle in which error of data is detected when the error detection unit detects the occurrence of error in data read out from the first storage unit by the load request; and an instruction execution unit that retransmits the load request to the first storage unit when data in which error is detected and a rerun request are given.

Abstract: A processor includes a storage unit storing an instruction, an instruction extension information register that includes a first area and a second area, an instruction decoding unit that decodes a first prefix instruction including first extension information extending an immediately following instruction written to the first area when the first prefix instruction is executed, and that decodes a second prefix instruction including the first extension information and a second extension information extending an instruction immediately following two instructions of the second prefix instruction, an instruction packing unit that generates a packed instruction including at least one of the first prefix instruction or the second prefix instruction, and the instruction immediately following the first prefix instruction or the second prefix instruction when the instruction decoding unit decodes the first prefix instruction or the second prefix instruction, an instruction execution unit that executes the packed instruc

Abstract: A processor is provided that is capable of concurrently processing a sequence of instructions for a plurality of threads achieving the retry success rate equivalent to the success rate in processors that process a sequence of instructions for a single thread. An arithmetic device 200 is provided with an instruction execution circuit 201 for executing a plurality of threads, or an execution control circuit 202 for controlling the execution state or rerunning of the threads.

Abstract: An arithmetic device simultaneously processes a plurality of threads and may continue the process by minimizing the degradation of the entire performance although a hardware error occurs. An arithmetic device 100 includes: an instruction execution circuit 101 capable of selectively executing a mode in which the instruction sequences of a plurality of threads are executed and a mode in which the instruction sequence of a single thread is executed; and a switch indication circuit 102 instructing the instruction execution circuit 101 to switch a thread mode.

Abstract: When two threads (strands), for example, are executed in parallel in a processor in a simultaneous multi-thread (SMT) system, entries of a branch reservation station of an instruction control device are separately used in a strand 0 group and a strand 1 group. The data of the strand 0 and the data of the strand 1 are allocated to the respective entries by switching a select circuit. When an entry is released from the branch reservation station, the select circuit switches the strands so that a branch instruction in one strand can be released in order, thereby releasing the entry.

Abstract: A processor including: a first storage unit that stores data; an error detection unit that detects an occurrence of error in data read out from the first storage unit; a second storage unit that stores data read out from the first storage unit based on a load request; a rerun request generation unit that generates a rerun request of a load request to the first storage unit in the same cycle as the cycle in which error of data is detected when the error detection unit detects the occurrence of error in data read out from the first storage unit by the load request; and an instruction execution unit that retransmits the load request to the first storage unit when data in which error is detected and a rerun request are given.

Abstract: A processor includes a storage unit storing an instruction, an instruction extension information register that includes a first area and a second area, an instruction decoding unit that decodes a first prefix instruction including first extension information extending an immediately following instruction written to the first area when the first prefix instruction is executed, and that decodes a second prefix instruction including the first extension information and a second extension information extending an instruction after two instructions written to the second area respectively, an instruction packing unit that generates a packed instruction including at least one of the first prefix instruction or the second prefix instruction, and the instruction immediately following the first prefix instruction or the second prefix instruction when the instruction decoding unit decodes the first prefix instruction or the second prefix instruction, an instruction execution unit that executes the packed instruction gene

Abstract: An instruction control device connects to a cache memory that stores data frequently used among data stored in a main memory. The instruction control device includes: a first free-space determining unit that determines whether there is free space in an instruction buffer; a second free-space determining unit that manages an instruction fetch request queue that stores an instruction fetch data to be sent from the cache memory to the main memory, and determines whether a move-in buffer in the cache memory has free space for at least two entries if the first free-space determining unit determines that there is free space; and an instruction control unit that outputs an instruction prefetch request to the cache memory in accordance with an address boundary corresponding to a line size of the cache line, if the second free-space determining unit determines that the move-in buffer has free space.

Abstract: A program counter control method controls instructions by an out-of-order method using a branch prediction mechanism and controls an architecture having delay instructions for branching. The method includes the steps of simultaneously committing a plurality of instructions including a branch instruction, when a branch prediction is successful and the branch instruction branches, and simultaneously updating a program counter and a next program counter depending on a number of committed instructions.

Abstract: An arithmetic device simultaneously processes a plurality of threads and may continue the process by minimizing the degradation of the entire performance although a hardware error occurs. An arithmetic device 100 includes: an instruction execution circuit 101 capable of selectively executing a mode in which the instruction sequences of a plurality of threads are executed and a mode in which the instruction sequence of a single thread is executed; and a switch indication circuit 102 instructing the instruction execution circuit 101 to switch a thread mode.

Abstract: A processor is provided that is capable of concurrently processing a sequence of instructions for a plurality of threads achieving the retry success rate equivalent to the success rate in processors that process a sequence of instructions for a single thread. An arithmetic device 200 is provided with an instruction execution circuit 201 for executing a plurality of threads, or an execution control circuit 202 for controlling the execution state or rerunning of the threads.

Abstract: When two threads (strands), for example, are executed in parallel in a processor in a simultaneous multi-thread (SMT) system, entries of a branch reservation station of an instruction control device are separately used in a strand 0 group and a strand 1 group. The data of the strand 0 and the data of the strand 1 are allocated to the respective entries by switching a select circuit. When an entry is released from the branch reservation station, the select circuit switches the strands so that a branch instruction in one strand can be released in order, thereby releasing the entry.

Abstract: An apparatus includes a branch instruction prediction unit configured to make branch prediction, and a branch prediction control unit configured to control an instruction fetch control unit, an instruction buffer, an instruction decoder, and the branch instruction prediction unit, wherein when the branch prediction control unit ascertains that the branch prediction by the branch instruction prediction unit is erroneous, the branch prediction control unit outputs to the instruction fetch control unit a signal for suppressing an instruction fetch request already supplied to the memory unit and outputs to the instruction buffer a signal for nullifying the instruction buffer during a period between a point in time at which the ascertainment is made by the branch prediction control unit that the branch prediction by the branch instruction prediction unit is erroneous and a point in time at which the instruction buffer fetches a correct instruction from the memory unit.

Abstract: An instruction control method carries out an instruction in a processor to process instructions by out-of-order processing, using delay instructions for branching. The processor includes a storage unit, a branch predictor making branch predictions and a control unit which successively stores a plurality of delay instructions in the storage unit together with information indicating whether or not branch instructions corresponding to the delay instructions are predicted to branch by the branch predictor.

Abstract: The branch instruction control apparatus of the present invention is a control apparatus in which a plurality of entries in which data required for the implementation control of the branch instructions is stored in order of decoding successively from the top entry, and said apparatus comprises a mechanism which, when one or more entries are successively released in order of older decoding from the top entry among the entries whose implementation control of the corresponding branch instruction has been completed, moves the contents of the remaining entries in a direction toward the top entry by the number of entries released, and a unit for storing data required for the implementation control of newly decoded branch instructions in one or more empty entries which are near the top entry including the entries which become empty by the movement, in the same cycle as in the movement of the said contents.

Abstract: In the out-of-order process of an instruction, the address mode information of a fetched branch instruction is automatically transferred from an instruction fetch pipeline to an instruction execution pipeline. If the branch instruction is accompanied by an address mode change, the address mode after change designated by the branch instruction is adopted as the address mode of a branch destination. If the branch instruction is not accompanied by an address mode change, the transferred address mode information is adopted as the address mode of the branch destination.

Abstract: The branch instruction control apparatus of the present invention is a control apparatus in which a plurality of entries in which data required for the implementation control of the branch instructions is stored in order of decoding successively from the top entry, and said apparatus comprises a mechanism which, when one or more entries are successively released in order of older decoding from the top entry among the entries whose implementation control of the corresponding branch instruction has been completed, moves the contents of the remaining entries in a direction toward the top entry by the number of entries released, and a unit for storing data required for the implementation control of newly decoded branch instructions in one or more empty entries which are near the top entry including the entries which become empty by the movement, in the same cycle as in the movement of the said contents.