Abstract: Signal propagation delay in an inverter chain having a first inverter cell and a second inverter cell connected by an intercell wire, is evaluated. In order to guarantee that a first inverter cell delay is always evaluated to be positive (A) a logic threshold voltage for an increase in input pin voltage of the first inverter cell is set to a voltage below a switching threshold voltage of the first inverter cell, and (B) a logic threshold voltage for a decrease in input pin voltage of the first inverter cell is set to a voltage above the switching threshold voltage of the first inverter cell. Similarly, logic threshold voltages for an increase and a decrease in input pin voltage of the second inverter cell are determined. Additionally, in order to guarantee that an intercell wire delay is always evaluated to be positive, logic threshold voltages for an output pin voltage of the first inverter cell are made to agree with the logic threshold voltages for the input pin voltage of the second inverter cell.

Abstract: After limited in band area with a vertical or horizontal low-pass filter in a sub-sampling circuit at the image-signal transmitting side, an image signal is sub-sampled as inter-frame offset in the form of a quincunx, and then transmitted to an image-signal receiving side through a transmission system. The sampling rate of the image signal thus received is converted by a sampling rate conversion portion. According to the operation of a changeover switch by the operator who watches a Braun tube for image reproduction, a selector selects the image signal interpolated with a vertical filter of a low-pass portion when the sub-sampling circuit uses a vertical filter, or the image signal interpolated with both vertical and horizontal low-pass filters when the sub-sampling circuit uses a two dimensional filter.

Abstract: A physical memory allocation system comprising an area estimation section, a program modification section, a program size read-in section, a memory size read-in section, a user control table, a size compare section, and an area allocation section. The area estimation section, after a program has been run for a predetermined period of time, measures a memory area size referred to by the program (i.e. the program size). The program modification section writes the program size to the program. The program size read-in section inputs the program size and the memory size read-in section inputs a user allocation size held at the user control table at program execution time. The size compare section makes a comparison in size between the user allocation size and the program size thereby outputting one of these two sizes that is found to be smaller than the other as an at-execution-time size. In the area allocation section, an amount of physical memory that a program can use is taken as an at-execution-time size.

Abstract: By reacting Si(OR).sub.4 with HF, FSi (OR).sub.3 of high purity can be obtained easily and economically.

Abstract: In a standard cell LSI including functional circuits formed by placing a group of cell rows consisting of standard cells selected from a group of standard cells and by routing the standard cells, a standard cell LSI layout method including the steps of comparing the routing density in routing areas located between the cell rows and bending the cell rows by shifting one or more of the standard cells in a direction of a more dispersed routing area from a more congested routing area. The cell rows are bent at a point between each high congested area of the routing area which encloses the cell rows depending on the routing density. A link cell may be provided for linking power and ground pins of the standard cells which have been shifted in position and which compose the bent cell rows. The link cell may be stored in a library in a system of composing the cell rows by storing the standard cells in a library and referring to the standard cells from the library in defining a standard cell LSI layout.