Patents by Inventor Ryuji Hosokawa

Ryuji Hosokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8759971
    Abstract: A semiconductor apparatus in a preferred embodiment includes: a substrate; a first chip provided on the substrate; a solder bump formed on the first chip; a solder dam arranged in substantially a rectangular and annular manner outside around the solder bump on the first chip by alternately connecting four sides and four quarter or less arcs; an electrode pad placed outside of the solder dam in the first chip; a second chip provided on the first chip in electric connection to the first chip via the solder bump; and an under-fill material filling a clearance between the first chip and the second chip inside of the solder dam. Here, a difference between an inner diameter and an outer diameter of the arc is 60 ?m or more whereas the center radius of the arc is greater than 207.5 ?m.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryuji Hosokawa, Tsutomu Kojima, Tatsuo Shiotsuki
  • Publication number: 20120049355
    Abstract: A semiconductor apparatus in a preferred embodiment includes: a substrate; a first chip provided on the substrate; a solder bump formed on the first chip; a solder dam arranged in substantially a rectangular and annular manner outside around the solder bump on the first chip by alternately connecting four sides and four quarter or less arcs; an electrode pad placed outside of the solder dam in the first chip; a second chip provided on the first chip in electric connection to the first chip via the solder bump; and an under-fill material filling a clearance between the first chip and the second chip inside of the solder dam. Here, a difference between an inner diameter and an outer diameter of the arc is 60 ?m or more whereas the center radius of the arc is greater than 207.5 ?m.
    Type: Application
    Filed: August 26, 2011
    Publication date: March 1, 2012
    Inventors: Ryuji HOSOKAWA, Tsutomu KOJIMA, Tatsuo SHIOTSUKI
  • Patent number: 7608911
    Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: October 27, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
  • Publication number: 20080265443
    Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.
    Type: Application
    Filed: June 24, 2008
    Publication date: October 30, 2008
    Applicant: Kabushiki Kaisha Toshiba,
    Inventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
  • Patent number: 7405159
    Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: July 29, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
  • Patent number: 7298035
    Abstract: A semiconductor device includes a substrate having first and second surfaces, the substrate having an opening; a first adhesive layer provided on the first surface; a second adhesive layer provided under the second surface; a third adhesive layer provided around the opening; a semiconductor chip arranging a plurality of chip bonding pads in a central portion of the semiconductor chip and adhered on the third adhesive layer; substrate bonding pads adhered under the second adhesive layer; bonding wires connecting the chip bonding pads to the substrate bonding pads; and an encapsulating resin provided around the semiconductor chip.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: November 20, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryuji Hosokawa, Takashi Imoto
  • Publication number: 20070196956
    Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.
    Type: Application
    Filed: March 1, 2007
    Publication date: August 23, 2007
    Inventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
  • Patent number: 7202563
    Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: April 10, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
  • Publication number: 20060055061
    Abstract: A semiconductor device includes a substrate having first and second surfaces, the substrate having an opening; a first adhesive layer provided on the first surface; a second adhesive layer provided under the second surface; a third adhesive layer provided around the opening; a semiconductor chip arranging a plurality of chip bonding pads in a central portion of the semiconductor chip and adhered on the third adhesive layer; substrate bonding pads adhered under the second adhesive layer; bonding wires connecting the chip bonding pads to the substrate bonding pads; and an encapsulating resin provided around the semiconductor chip.
    Type: Application
    Filed: September 1, 2005
    Publication date: March 16, 2006
    Inventors: Ryuji Hosokawa, Takashi Imoto
  • Publication number: 20050212145
    Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.
    Type: Application
    Filed: March 25, 2005
    Publication date: September 29, 2005
    Inventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
  • Patent number: 6734541
    Abstract: A semiconductor laminated module comprises a plurality of unit packages in which semiconductor chips are bonded to base substrates with a first adhesive, a second adhesive to form a laminated body by bonding the plurality of unit packages to each other, a third adhesive formed to cover an upper surface of the semiconductor chips and having substantially the same thermal expansion coefficient as that of the first adhesive, and an uppermost substrate bonded to uppermost one of the unit packages with the second adhesive.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: May 11, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Shimoe, Naohisa Okumura, Takashi Imoto, Ryuji Hosokawa
  • Publication number: 20020190368
    Abstract: A semiconductor laminated module comprises a plurality of unit packages in which semiconductor chips are bonded to base substrates with a first adhesive, a second adhesive to form a laminated body by bonding the plurality of unit packages to each other, a third adhesive formed to cover an upper surface of the semiconductor chips and having substantially the same thermal expansion coefficient as that of the first adhesive, and an uppermost substrate bonded to uppermost one of the unit packages with the second adhesive.
    Type: Application
    Filed: June 18, 2002
    Publication date: December 19, 2002
    Applicant: KABUSHIKI KAISHI TOSHIBA
    Inventors: Hiroshi Shimoe, Naohisa Okumura, Takashi Imoto, Ryuji Hosokawa
  • Patent number: 5614441
    Abstract: A method of manufacturing a semiconductor device wherein, a first lead frame portion has a bed portion for mounting a semiconductor element and a plurality of inner and outer leads. A second lead frame portion has a bed portion for mounting a semiconductor element and a plurality of inner and outer leads as in the first lead frame portion coupled to the second lead frame portion through a coupling portion. The first and second lead frame portions are folded at the coupling portion and superposed such that the two semiconductor elements oppose each other. At this time, the plurality of inner and outer leads of the first and second lead frames are alternately and adjacently arranged. Each electrode of the semiconductor elements is connected to a corresponding inner lead. The superposed first and second lead frames are sealed with a mold resin while leaving end portions of the plurality of outer leads of the first and second lead frames.
    Type: Grant
    Filed: May 4, 1995
    Date of Patent: March 25, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryuji Hosokawa, Satoru Yanagida
  • Patent number: 5543658
    Abstract: According to a method of manufacturing a semiconductor device of this invention, a first lead frame portion has a bed portion for mounting a semiconductor element and a plurality of inner and outer leads. A second lead frame portion has a bed portion for mounting a semiconductor element and a plurality of inner and outer leads as in the first lead frame portion coupled to the second lead frame portion through a coupling portion. The first and second lead frame portions are folded at the coupling portion and superposed each other such that the two semiconductor elements oppose each other. At this time, the plurality of inner and outer leads of the first and second lead frames are alternately and adjacently arranged. Each electrode of the semiconductor elements is connected to a corresponding inner lead. The superposed first and second lead frames are sealed with a mold resin while leaving end portions of the plurality of outer leads of the first and second lead frames.
    Type: Grant
    Filed: March 16, 1994
    Date of Patent: August 6, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryuji Hosokawa, Satoru Yanagida