Patents by Inventor Ryuji Hosokawa
Ryuji Hosokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8759971Abstract: A semiconductor apparatus in a preferred embodiment includes: a substrate; a first chip provided on the substrate; a solder bump formed on the first chip; a solder dam arranged in substantially a rectangular and annular manner outside around the solder bump on the first chip by alternately connecting four sides and four quarter or less arcs; an electrode pad placed outside of the solder dam in the first chip; a second chip provided on the first chip in electric connection to the first chip via the solder bump; and an under-fill material filling a clearance between the first chip and the second chip inside of the solder dam. Here, a difference between an inner diameter and an outer diameter of the arc is 60 ?m or more whereas the center radius of the arc is greater than 207.5 ?m.Type: GrantFiled: August 26, 2011Date of Patent: June 24, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Ryuji Hosokawa, Tsutomu Kojima, Tatsuo Shiotsuki
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Publication number: 20120049355Abstract: A semiconductor apparatus in a preferred embodiment includes: a substrate; a first chip provided on the substrate; a solder bump formed on the first chip; a solder dam arranged in substantially a rectangular and annular manner outside around the solder bump on the first chip by alternately connecting four sides and four quarter or less arcs; an electrode pad placed outside of the solder dam in the first chip; a second chip provided on the first chip in electric connection to the first chip via the solder bump; and an under-fill material filling a clearance between the first chip and the second chip inside of the solder dam. Here, a difference between an inner diameter and an outer diameter of the arc is 60 ?m or more whereas the center radius of the arc is greater than 207.5 ?m.Type: ApplicationFiled: August 26, 2011Publication date: March 1, 2012Inventors: Ryuji HOSOKAWA, Tsutomu KOJIMA, Tatsuo SHIOTSUKI
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Patent number: 7608911Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.Type: GrantFiled: June 24, 2008Date of Patent: October 27, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
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Publication number: 20080265443Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.Type: ApplicationFiled: June 24, 2008Publication date: October 30, 2008Applicant: Kabushiki Kaisha Toshiba,Inventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
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Patent number: 7405159Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.Type: GrantFiled: March 1, 2007Date of Patent: July 29, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
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Patent number: 7298035Abstract: A semiconductor device includes a substrate having first and second surfaces, the substrate having an opening; a first adhesive layer provided on the first surface; a second adhesive layer provided under the second surface; a third adhesive layer provided around the opening; a semiconductor chip arranging a plurality of chip bonding pads in a central portion of the semiconductor chip and adhered on the third adhesive layer; substrate bonding pads adhered under the second adhesive layer; bonding wires connecting the chip bonding pads to the substrate bonding pads; and an encapsulating resin provided around the semiconductor chip.Type: GrantFiled: September 1, 2005Date of Patent: November 20, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Ryuji Hosokawa, Takashi Imoto
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Publication number: 20070196956Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.Type: ApplicationFiled: March 1, 2007Publication date: August 23, 2007Inventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
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Patent number: 7202563Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.Type: GrantFiled: March 25, 2005Date of Patent: April 10, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
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Publication number: 20060055061Abstract: A semiconductor device includes a substrate having first and second surfaces, the substrate having an opening; a first adhesive layer provided on the first surface; a second adhesive layer provided under the second surface; a third adhesive layer provided around the opening; a semiconductor chip arranging a plurality of chip bonding pads in a central portion of the semiconductor chip and adhered on the third adhesive layer; substrate bonding pads adhered under the second adhesive layer; bonding wires connecting the chip bonding pads to the substrate bonding pads; and an encapsulating resin provided around the semiconductor chip.Type: ApplicationFiled: September 1, 2005Publication date: March 16, 2006Inventors: Ryuji Hosokawa, Takashi Imoto
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Publication number: 20050212145Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.Type: ApplicationFiled: March 25, 2005Publication date: September 29, 2005Inventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
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Patent number: 6734541Abstract: A semiconductor laminated module comprises a plurality of unit packages in which semiconductor chips are bonded to base substrates with a first adhesive, a second adhesive to form a laminated body by bonding the plurality of unit packages to each other, a third adhesive formed to cover an upper surface of the semiconductor chips and having substantially the same thermal expansion coefficient as that of the first adhesive, and an uppermost substrate bonded to uppermost one of the unit packages with the second adhesive.Type: GrantFiled: June 18, 2002Date of Patent: May 11, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shimoe, Naohisa Okumura, Takashi Imoto, Ryuji Hosokawa
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Publication number: 20020190368Abstract: A semiconductor laminated module comprises a plurality of unit packages in which semiconductor chips are bonded to base substrates with a first adhesive, a second adhesive to form a laminated body by bonding the plurality of unit packages to each other, a third adhesive formed to cover an upper surface of the semiconductor chips and having substantially the same thermal expansion coefficient as that of the first adhesive, and an uppermost substrate bonded to uppermost one of the unit packages with the second adhesive.Type: ApplicationFiled: June 18, 2002Publication date: December 19, 2002Applicant: KABUSHIKI KAISHI TOSHIBAInventors: Hiroshi Shimoe, Naohisa Okumura, Takashi Imoto, Ryuji Hosokawa
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Patent number: 5614441Abstract: A method of manufacturing a semiconductor device wherein, a first lead frame portion has a bed portion for mounting a semiconductor element and a plurality of inner and outer leads. A second lead frame portion has a bed portion for mounting a semiconductor element and a plurality of inner and outer leads as in the first lead frame portion coupled to the second lead frame portion through a coupling portion. The first and second lead frame portions are folded at the coupling portion and superposed such that the two semiconductor elements oppose each other. At this time, the plurality of inner and outer leads of the first and second lead frames are alternately and adjacently arranged. Each electrode of the semiconductor elements is connected to a corresponding inner lead. The superposed first and second lead frames are sealed with a mold resin while leaving end portions of the plurality of outer leads of the first and second lead frames.Type: GrantFiled: May 4, 1995Date of Patent: March 25, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Ryuji Hosokawa, Satoru Yanagida
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Patent number: 5543658Abstract: According to a method of manufacturing a semiconductor device of this invention, a first lead frame portion has a bed portion for mounting a semiconductor element and a plurality of inner and outer leads. A second lead frame portion has a bed portion for mounting a semiconductor element and a plurality of inner and outer leads as in the first lead frame portion coupled to the second lead frame portion through a coupling portion. The first and second lead frame portions are folded at the coupling portion and superposed each other such that the two semiconductor elements oppose each other. At this time, the plurality of inner and outer leads of the first and second lead frames are alternately and adjacently arranged. Each electrode of the semiconductor elements is connected to a corresponding inner lead. The superposed first and second lead frames are sealed with a mold resin while leaving end portions of the plurality of outer leads of the first and second lead frames.Type: GrantFiled: March 16, 1994Date of Patent: August 6, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Ryuji Hosokawa, Satoru Yanagida