Abstract: A reception circuit that receives data in serial communications through a plurality of lanes includes a plurality of buffers provided for each of the plurality of lanes that each stores data received through corresponding lane, a multilane control circuit that detects the skew between the lanes, and outputs an adjustment instruction for adjusting a read address of a buffer and a deskew information indicating that a skew adjustment between which buffer the lanes is to be performed based on the detected skew, and a plurality of address control circuits provided for each of the plurality of lanes that each transmits the adjustment instruction to a corresponding buffer when receiving the deskew information, wherein the buffer that has received the adjustment instruction adjusting its read address.

Abstract: A reception apparatus that receives data through a plurality of lanes and includes a plurality of buffers that store received data, the buffers being provided for each of the plurality of lanes; a speed difference controller outputs a first timing signal for adjusting timing among the lanes, based on a communication speed on the lanes and operational clocks for the transmission apparatus and the reception apparatus; a deskew controller that outputs a second timing signal for adjusting a skew among the lanes; and a controller that adjusts timing for reading the received data from the buffers, based on a value of the second timing signal and a difference between a read position for reading the received data from the buffers and a write position for writing the received data to the buffers, in the first timing signal, upon adjusting a frequency difference between the transmission apparatus and the reception apparatus.

Abstract: In a storage apparatus: a write-address counter outputs a write address; an input-data inverter inverts input data to be inputted into a storage unit; an input-data selector selects one of the input data and the inverted input data on the basis of one or more first bits constituting the write address, and writes the one of the input data and the inverted input data in the storage unit on the basis of one or more second bits constituting the write address; a read-address counter outputs the read address; an output-data inverter inverts output data outputted from the storage unit on the basis of one or more third bits constituting the read address; and an output-data selector selects and outputs one of the output data and the inverted output data on the basis of one or more fourth bits constituting the read address.

Abstract: An information processing apparatus includes a control information generating unit configured to generate second control information transferred and received on a physical layer of a communication line on the basis of an error on the physical layer of the communication line or an error on a data link layer initialized by use of first control information of the physical layer, and a transmitting unit configured to transmit the second control information generated by the control information generating unit via the physical layer of the communication line when a communication on the data link layer of the communication line is disabled.

Abstract: A data transfer apparatus includes a plurality of transmitting units. The data transfer apparatus includes a detecting unit that detects a malfunction in any of the transfer paths. The data transfer apparatus includes a selecting unit that, when one or more malfunctions have been detected by the detecting unit, selects a predetermined number of transmitting units from among such transmitting units that transmit data via transfer paths in which no malfunction is detected by the detecting unit. The data transfer apparatus includes a generating unit that generates redundancy data used for detecting errors. The data transfer apparatus includes an assigning unit that assigns the data to transmitting units remaining after excluding one transmitting unit from the transmitting units selected by the selecting unit and assigns the redundancy data generated by the generating unit to the excluded transmitting unit.

Abstract: A data transfer system transfers data via a plurality of signal lines and controls to select the signal lines to adapt reduction and lane reversal. The signal line control unit has a signal creation unit that creates a first selection signal when the signal lines are reduced according to the abnormal detection from the abnormal detection unit, and a signal output unit that outputs a second selection signal when a connection of the second selection signal indicating that any one or both signal line of a second pair of signal lines is changed in case of a lane reversal that connects a plurality of signal lines in a down order from a highest bit to a lowest bit of a sending device side with a plurality of signal in a up order from a highest bit to a lowest bit of a reception device side.

Abstract: A serial data receiver circuit apparatus to receive serial data delimited by a first bit length, the circuit apparatus includes: a serial/parallel converter circuit to convert the serial data into parallel data of a second bit length that is smaller than the first bit length; a data hold circuit to hold a plurality of parallel data; a detector circuit to detect a delimiter position in the received serial data; a detected position hold circuit to generate a select signal to select data included in the parallel data stored in the data hold circuit; and a selector circuit to select data in units of the second bit length starting from the data delimiter position based on the select signal.

Abstract: In a storage apparatus: a write-address counter outputs a write address; an input-data inverter inverts input data to be inputted into a storage unit; an input-data selector selects one of the input data and the inverted input data on the basis of one or more first bits constituting the write address, and writes the one of the input data and the inverted input data in the storage unit on the basis of one or more second bits constituting the write address; a read-address counter outputs the read address; an output-data inverter inverts output data outputted from the storage unit on the basis of one or more third bits constituting the read address; and an output-data selector selects and outputs one of the output data and the inverted output data on the basis of one or more fourth bits constituting the read address.

Abstract: A data transfer system transfers data via a plurality of signal lines and controls to select the signal lines to adapt reduction and lane reversal. The signal line control unit has a signal creation unit that creates a first selection signal when the signal lines are reduced according to the abnormal detection from the abnormal detection unit, and a signal output unit that outputs a second selection signal when a connection of the second selection signal indicating that any one or both signal line of a second pair of signal lines is changed in case of a lane reversal that connects a plurality of signal lines in a down order from a highest bit to a lowest bit of a sending device side with a plurality of signal in a up order from a highest bit to a lowest bit of a reception device side.

Abstract: A serial data receiver circuit apparatus to receive serial data delimited by a first bit length, the circuit apparatus includes: a serial/parallel converter circuit to convert the serial data into parallel data of a second bit length that is smaller than the first bit length; a data hold circuit to hold a plurality of parallel data; a detector circuit to detect a delimiter position in the received serial data; a detected position hold circuit to generate a select signal to select data included in the parallel data stored in the data hold circuit; and a selector circuit to select data in units of the second bit length starting from the data delimiter position based on the select signal.

Abstract: A reception circuit that receives data in serial communications through a plurality of lanes includes a plurality of buffers provided for each of the plurality of lanes that each stores data received through corresponding lane, a multilane control circuit that detects the skew between the lanes, and outputs an adjustment instruction for adjusting a read address of a buffer and a deskew information indicating that a skew adjustment between which buffer the lanes is to be performed based on the detected skew, and a plurality of address control circuits provided for each of the plurality of lanes that each transmits the adjustment instruction to a corresponding buffer when receiving the deskew information, wherein the buffer that has received the adjustment instruction adjusting its read address.

Abstract: Provided is a data transfer apparatus having a system bus interface 20 connected to an MC 51, a high-speed I/O bus interface connected to a high-speed I/O bus switch 54, a history selection controller 10 that selects part of transmission/reception data transferred between the MC 51 and high-speed I/O bus switch 54, a buffer section 11 that is connected to the history selection controller 10 and retains the part of the transmission/reception data selected by the history selection controller 10, and a low-speed bus interface that outputs the part of the transmission/reception data retained by the buffer section 11 to an observation apparatus 200.

Abstract: Provided is a data transfer apparatus having a system bus interface 20 connected to an MC 51, a high-speed I/O bus interface connected to a high-speed I/O bus switch 54, a history selection controller 10 that selects part of transmission/reception data transferred between the MC 51 and high-speed I/O bus switch 54, a buffer section 11 that is connected to the history selection controller 10 and retains the part of the transmission/reception data selected by the history selection controller 10, and a low-speed bus interface that outputs the part of the transmission/reception data retained by the buffer section 11 to an observation apparatus 200.