Patents by Inventor Ryuji Kono

Ryuji Kono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090209053
    Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multilayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multilayer film. A clamping member is provided on the frame to make the multilayer film project out to eliminate slack in the multilayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.
    Type: Application
    Filed: March 20, 2009
    Publication date: August 20, 2009
    Inventors: Susumu KASUKABE, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Patent number: 7541202
    Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: June 2, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Publication number: 20080009082
    Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.
    Type: Application
    Filed: September 12, 2007
    Publication date: January 10, 2008
    Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Patent number: 7285430
    Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: October 23, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Patent number: 7214271
    Abstract: A silicon single crystal wafer process apparatus (10) having: a process chamber (11); a susceptor (12) which is disposed in the process chamber (11), and on an upper surface of which the silicon single crystal wafer (19) is placed; and a lift pin (14) which is provided to be capable of a going up and down operation with respect to the susceptor (12), for attaching or detaching the silicon single crystal wafer (19) to or from the susceptor (12) with the going up and down operation, in a state to support the silicon single crystal wafer (19) from a lower surface side, wherein the lift pin (14) is subjected to polishing on a contact end surface (14d) which contacts with a rear surface of the silicon single crystal wafer (19).
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: May 8, 2007
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Ryuji Kono, Shoichi Takamizawa
  • Patent number: 7119362
    Abstract: In an electric characteristic testing process corresponding to a process of the semiconductor apparatus manufacturing processes, in order to test a large area of the electrode pad of the body to be tested in a lump, an electric characteristic testing is performed by pressing a testing structure provided with electrically independent projections having a number equal to a number of conductor portions to be tested formed on an area to be tested of a body to be tested to the body to be tested.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: October 10, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Ryuji Kono, Makoto Kitano, Hideo Miura, Hiroyuki Ota, Yoshishige Endo, Takeshi Harada, Masatoshi Kanamaru, Teruhisa Akashi, Atsushi Hosogane, Akihiko Ariga, Naoto Ban
  • Publication number: 20040241992
    Abstract: A silicon single crystal wafer process apparatus (10) having: a process chamber (11); a susceptor (12) which is disposed in the process chamber (11), and on an upper surface of which the silicon single crystal wafer (19) is placed; and a lift pin (14) which is provided to be capable of a going up and down operation with respect to the susceptor (12), for attaching or detaching the silicon single crystal wafer (19) to or from the susceptor (12) with the going up and down operation, in a state to support the silicon single crystal wafer (19) from a lower surface side, wherein the lift pin (14) is subjected to polishing on a contact end surface (14d) which contacts with a rear surface of the silicon single crystal wafer (19).
    Type: Application
    Filed: March 18, 2004
    Publication date: December 2, 2004
    Inventors: Ryuji Kono, Shoichi Takamizawa
  • Publication number: 20040235207
    Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.
    Type: Application
    Filed: June 23, 2004
    Publication date: November 25, 2004
    Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Patent number: 6759258
    Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: July 6, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Patent number: 6626994
    Abstract: There are provided a silicon wafer for epitaxial growth wherein a void type defect is not exposed on the surface where an epitaxial layer is grown, and a method for producing an epitaxial wafer comprising measuring the number of the void type defects exposed on the surface of a silicon wafer and/or the number of the void type defects which exist in the part to the depth of at least 10 nm from the surface of the silicon wafer, choosing the silicon wafer wherein the number of these void type defects is smaller than the predetermined value, and growing an epitaxial layer on the surface of the chosen silicon wafer. Thereby, there can be provided a silicon wafer for epitaxial growth wherein generation of SF is reduced and epitaxial wafer, and a method for producing it.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: September 30, 2003
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Akihiro Kimura, Hideki Sato, Ryuji Kono, Masahiro Kato, Masaro Tamatsuka
  • Patent number: 6573112
    Abstract: Semiconductor device chips manufacturing and inspecting method is disclosed in which a semiconductor wafer is cut into individual LSI chips. The LSI chips are rearranged and integrated into a predetermined number. The cut LSI chips are integrated in a jig having openings with a size commensurate with the dimensions of the LSI chip. At least one part of the jig having such openings has a coefficient of thermal expansion that is approximately equal to that of the LSI chips. The integrated predetermined number of chips are subjected to an inspection process in a subsequent inspection step thereby improving efficiency and reducing cost.
    Type: Grant
    Filed: September 11, 2002
    Date of Patent: June 3, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kono, Akihiko Ariga, Hideyuki Aoki, Hiroyuki Ohta, Yoshishige Endo, Masatoshi Kanamaru, Atsushi Hosogane, Shinji Tanaka, Naoto Ban, Hideo Miura
  • Publication number: 20030092206
    Abstract: In an electric characteristic testing process corresponding to a process of the semiconductor apparatus manufacturing processes, in order to test a large area of the electrode pad of the body to be tested in a lump, an electric characteristic testing is performed by pressing a testing structure provided with electrically independent projections having a number equal to a number of conductor portions to be tested formed on an area to be tested of a body to be tested to the body to be tested.
    Type: Application
    Filed: December 23, 2002
    Publication date: May 15, 2003
    Inventors: Ryuji Kono, Makoto Kitano, Hideo Miura, Hiroyuki Ota, Yoshishige Endo, Takeshi Harada, Masatoshi Kanamaru, Teruhisa Akashi, Atsushi Hosogane, Akihiko Ariga, Naoto Ban
  • Publication number: 20030027365
    Abstract: [Problem] To provide a semiconductor device manufacturing method and a semiconductor device inspection method both of which are capable of efficiently inspecting individual LSI chips separated by cutting, as well as a jig for use in such methods.
    Type: Application
    Filed: September 11, 2002
    Publication date: February 6, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Ryuji Kono, Akihiko Ariga, Hideyuki Aoki, Hiroyuki Ohta, Yoshishige Endo, Masatoshi Kanamaru, Atsushi Hosogane, Shinji Tanaka, Naoto Ban, Hideo Miura
  • Patent number: 6511857
    Abstract: In an electric characteristic testing process corresponding to a process of the semiconductor apparatus manufacturing processes, in order to test a large area of the electrode pad of the body to be tested in a lump, an electric characteristic testing is performed by pressing a testing structure provided with electrically independent projections having a number equal to a number of conductor portions to be tested formed on an area to be tested of a body to be tested to the body to be tested.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: January 28, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kono, Makoto Kitano, Hideo Miura, Hiroyuki Ota, Yoshishige Endo, Takeshi Harada, Masatoshi Kanamaru, Teruhisa Akashi, Atsushi Hosogane, Akihiko Ariga, Naoto Ban
  • Patent number: 6479305
    Abstract: Semiconductor device chips manufacturing and inspecting method is disclosed in which a semiconductor wafer is cut into individual LSI chips. The LSI chips are rearranged and integrated into a predetermined number. The cut LSI chips are integrated in a jig having openings with a size commensurate with the dimensions of the LSI chip. At least one part of the jig having such openings has a coefficient of thermal expansion that is approximately equal to that of the LSI chips. The integrated predetermined number of chips are subjected to an inspection process in a subsequent inspection step thereby improving efficiency and reducing cost.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: November 12, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kono, Akihiko Ariga, Hideyuki Aoki, Hiroyuki Ohta, Yoshishige Endo, Masatoshi Kanamaru, Atsushi Hosogane, Shinji Tanaka, Naoto Ban, Hideo Miura
  • Publication number: 20020129323
    Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.
    Type: Application
    Filed: October 9, 2001
    Publication date: September 12, 2002
    Inventors: Susumu Kasukabe, Terutaka Mori, Akihiko Ariga, Hidetaka Shigi, Takayoshi Watanabe, Ryuji Kono
  • Publication number: 20020064893
    Abstract: [Problem] To provide a semiconductor device manufacturing method and a semiconductor device inspection method both of which are capable of efficiently inspecting individual LSI chips separated by cutting, as well as a jig for use in such methods. [Means for Resolution] After a multiplicity of LSI chips are cut and separated from one semiconductor wafer, in the step of inspecting LSI chips, a predetermined number N of chips are rearranged and integrated by using a jig for integration which is formed of a material whose coefficient of thermal expansion approximates that of the chips and in which is formed an accommodating portion for rearranging the predetermined number N of chips, and the integrated predetermined number N of chips are subjected to a predetermined inspection process in a subsequent inspection step, whereby inspection efficiency is improved and inspection costs are reduced.
    Type: Application
    Filed: September 15, 1999
    Publication date: May 30, 2002
    Inventors: RYUJI KONO, AKIHIKO ARIGA, HIDEO MIURA, HIROYUKI OHTA, YOSHISHIGE ENDO, MASATOSHI KANAMARU, ATSUSHI HOSOGANE, SHINJI TANAKA, NAOTO BAN, HIDEYUKI AOKI
  • Patent number: D642978
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: August 9, 2011
    Assignee: Hitachi Vehicle Energy, Ltd
    Inventors: Yutaka Sato, Ryuji Kono, Mitsuru Koseki, Hidemasa Kawai, Hideyuki Shibanuma, Naoki Kimura, Keisuke Sawada, Fujio Hirano, Takuro Tsunaki, Takenori Ishizu, Kiyoyuki Sekine, Kinya Aota, Kouichi Kajiwara, Sho Saimaru
  • Patent number: D644176
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: August 30, 2011
    Assignee: Hitachi Vehicle Energy, Ltd.
    Inventors: Yutaka Sato, Ryuji Kono, Mitsuru Koseki, Hidemasa Kawai, Hideyuki Shibanuma, Naoki Kimura, Keisuke Sawada, Fujio Hirano, Takuro Tsunaki, Takenori Ishizu, Kiyoyuki Sekine, Kinya Aota, Kouichi Kajiwara, Sho Saimaru
  • Patent number: D644178
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: August 30, 2011
    Assignee: Hitachi Vehicle Energy, Ltd.
    Inventors: Yutaka Sato, Ryuji Kono, Mitsuru Koseki, Hidemasa Kawai, Hideyuki Shibanuma, Naoki Kimura, Keisuke Sawada, Fujio Hirano, Takuro Tsunaki, Takenori Ishizu, Kiyoyuki Sekine, Kinya Aota, Kouichi Kajiwara, Sho Saimaru