Abstract: A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.

Abstract: A first transistor is connected in series with one end of a fuse element. A second transistor is connected in series with the other end of the fuse element. A current flows through the fuse element when both the first and second transistors are turned on.

Abstract: A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.

Abstract: A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.

Abstract: The invention provides an electrical fuse device comprising: a plurality of fuse cores, each having an electrical fuse element and a switching element serially connected to the electrical fuse element; a program control circuit generating a program shift signal by sequentially shifting a program control transmission signal in synchronization with an effective program clock signal and subsequently generating a program signal to be sent to each of the switching elements in the plurality of fuse cores based on program data and the program shift signal; and a program clock control circuit controlling the conducting and non-conducting states of a program clock signal in accordance with a program clock enable signal and, when the program clock signal is in a conducting state, transmitting the program clock signal to the program control circuit as the effective program clock signal.

Abstract: A first transistor is connected in series with one end of a fuse element. A second transistor is connected in series with the other end of the fuse element. A current flows through the fuse element when both the first and second transistors are turned on.

Abstract: Electrical fuse blocks (100) of a plurality of stages are provided each of which includes a plurality of electrical fuse cores (101). The electrical fuse block (100) includes a program shift register block (103) made up of shift registers (107) which are disposed for the respective electrical fuse cores (101), sequentially transmit program enable signal FPGI, and output the program enable signal FPGI to the NMOS transistors (105) of the electrical fuse cores (101). When performing programming according to programming decision signal PBn, the program shift register block (103) transmits the program enable signal FPGI. When not performing programming, the program shift register block (103) skips the program enable signal FPGI.

Abstract: The invention provides an electrical fuse device comprising: a plurality of fuse cores, each having an electrical fuse element and a switching element serially connected to the electrical fuse element; a program control circuit generating a program shift signal by sequentially shifting a program control transmission signal in synchronization with an effective program clock signal and subsequently generating a program signal to be sent to each of the switching elements in the plurality of fuse cores based on program data and the program shift signal; and a program clock control circuit controlling the conducting and non-conducting states of a program clock signal in accordance with a program clock enable signal and, when the program clock signal is in a conducting state, transmitting the program clock signal to the program control circuit as the effective program clock signal.

Abstract: An electrical fuse circuit of the present invention includes a plurality of electrical fuse cores (1) each of which has an electrical fuse element (3) and a switch transistor (4) connected in series with each other, and shift registers (2) connected to the plurality of electrical fuse cores (1) to program the electrical fuse elements (3). Program enable signals (Si) are sequentially generated and transferred by the shift registers (2), the switch transistors (4) are sequentially brought into conduct according to the program enable signals (Si) and the information of program data (Di), and the electrical fuse elements (3) are blown one by one.

Abstract: A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.

Abstract: A fuse device and a program transistor are connected in series with each other. A flip-flop turns ON, in response to a start signal, the program transistor to start program of the fuse device. A 2-input NAND circuit outputs an end signal at a time point where change in a resistance value of the fuse device is increased to reach a predetermined level while monitoring change in the resistance value of the fuse device through change in a voltage at a junction point of the fuse device and the program transistor. The flip-flop turns OFF, in response to the end signal, the program transistor to automatically terminate the program of the fuse device. Thus, the resistance value of the fuse device is increased to the predetermined level in a minimum program time.

Abstract: Selection signals output from a decoder are selectively set at High according to the states (blown or not blown) or fuses in bit cells in a cell group specifying circuit. Then, one of transistor gates is turned ON so that a data bit cell group in/from which data is written and read out is selected. Accordingly, stored data can be rewritten multiple times by sequentially blowing the fuses in the cell group specifying circuit.

Abstract: Provided is a semiconductor memory, comprising: a voltage converting circuit which voltage-converts a resistance difference between a first and a second resistance elements; a voltage comparing circuit which outputs an output corresponding to the voltage conversion; a latch circuit for holding the output of the voltage comparing circuit; and a switch circuit which cuts and connects the voltage converting circuit and the voltage comparing circuit.

Abstract: Electrical fuse blocks (100) of a plurality of stages are provided each of which includes a plurality of electrical fuse cores (101). The electrical fuse block (100) includes a program shift register block (103) made up of shift registers (107) which are disposed for the respective electrical fuse cores (101), sequentially transmit program enable signal FPGI, and output the program enable signal FPGI to the NMOS transistors (105) of the electrical fuse cores (101). When performing programming according to programming decision signal PBn, the program shift register block (103) transmits the program enable signal FPGI. When not performing programming, the program shift register block (103) skips the program enable signal FPGI.

Abstract: A semiconductor memory device includes: first and second bit cells for storing complementary data; a scan circuit for outputting a selected data signal; a bit-cell selector receiving the output of the scan circuit and selecting one of the bit cells; and a data write controlling circuit for controlling data writing. Write paths for all the bit cells for storing “0” are not selected and data is written only in a bit cell for storing “1”, so that write operation performed in steps is achieved.

Abstract: An electrical fuse circuit of the present invention includes a plurality of electrical fuse cores (1) each of which has an electrical fuse element (3) and a switch transistor (4) connected in series with each other, and shift registers (2) connected to the plurality of electrical fuse cores (1) to program the electrical fuse elements (3). Program enable signals (Si) are sequentially generated and transferred by the shift registers (2), the switch transistors (4) are sequentially brought into conduct according to the program enable signals (Si) and the information of program data (Di), and the electrical fuse elements (3) are blown one by one.

Abstract: A semiconductor integrated circuit device includes: first and second nonvolatile memory elements; a first amplifier for amplifying an output signal from the first nonvolatile memory element to output the amplified signal; and a second amplifier for outputting to the first amplifier a control signal generated by amplifying an output signal from the second nonvolatile memory element. The second amplifier fixes the output signal from the first amplifier at a high potential or a low potential based on data stored in the second nonvolatile memory element.

Abstract: Selection signals output from a decoder are selectively set at High according to the states (blown or not blown) or fuses in bit cells in a cell group specifying circuit. Then, one of transistor gates is turned ON so that a data bit cell group in/from which data is written and read out is selected. Accordingly, stored data can be rewritten multiple times by sequentially blowing the fuses in the cell group specifying circuit.

Abstract: In a normal operation, an output of a differential amplifier for amplifying a difference between first and second bit cells is output as readout data. In a test mode, when a first control signal is set to be “H”, the output of the differential amplifier is fixed to be “H” and thus an output of the first bit cell is read out through gates.

Abstract: A fuse device and a program transistor are connected in series with each other. A flip-flop turns ON, in response to a start signal, the program transistor to start program of the fuse device. A 2-input NAND circuit outputs an end signal at a time point where change in a resistance value of the fuse device is increased to reach a predetermined level while monitoring change in the resistance value of the fuse device through change in a voltage at a junction point of the fuse device and the program transistor. The flip-flop turns OFF, in response to the end signal, the program transistor to automatically terminate the program of the fuse device. Thus, the resistance value of the fuse device is increased to the predetermined level in a minimum program time.