Patents by Inventor Ryuji Nishikubo
Ryuji Nishikubo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230315292Abstract: According to one embodiment, a semiconductor storage device includes a volatile memory, nonvolatile memory chips, channels, nonvolatile memory interfaces, and a bus arbiter. Each of the channels is connected to at least one nonvolatile memory chip of the nonvolatile memory chips. Each of the nonvolatile memory interfaces is connected to at least one channel of the channels and controls the at least one nonvolatile memory chip via the connected channel. The bus arbiter controls use of a bus in data transfer between the volatile memory and each of the nonvolatile memory chips in accordance with a bandwidth of the bus.Type: ApplicationFiled: June 14, 2022Publication date: October 5, 2023Applicant: Kioxia CorporationInventors: Ryuji NISHIKUBO, Norio AOYAMA
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Patent number: 11416372Abstract: A storage device includes a hardware random number generator configured to generate a random number; a first memory; and a controller configured to control the hardware random number generator and the first memory. The controller is configured to: obtain the random number generated by the hardware random number generator after the storage device is powered up; obtain a first trace log of the storage device; and store, into the first memory, a log resulting from appending the obtained random number to the first trace log, as a second trace log.Type: GrantFiled: August 19, 2020Date of Patent: August 16, 2022Assignee: Kioxia CorporationInventors: Ryuji Nishikubo, Hirokuni Yano
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Patent number: 11347479Abstract: A memory system includes a nonvolatile memory and a controller that performs first, second, and third processes on memory cells of the nonvolatile memory. The first process is performed on first memory cells to store a first value therein, such that a highest threshold voltage among the threshold voltages of the first memory cells is set as a first threshold voltage. The second process is performed on second memory cells to store a second value therein, such that a lowest threshold voltage among the threshold voltages of the second memory cells is set as a second threshold voltage higher than the first threshold voltage. The third process performed on third memory cells such that a lowest threshold voltage in the third memory cells is lower than the first threshold voltage, and a highest threshold voltage in the third memory cells is higher than the second threshold voltage.Type: GrantFiled: February 26, 2020Date of Patent: May 31, 2022Assignee: KIOXIA CORPORATIONInventors: Mel Stychen Sanchez Tan, Aurelien Nam Phong Tran, Ryuji Nishikubo, Norio Aoyama
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Publication number: 20210294526Abstract: A storage device includes a hardware random number generator configured to generate a random number; a first memory; and a controller configured to control the hardware random number generator and the first memory. The controller is configured to: obtain the random number generated by the hardware random number generator after the storage device is powered up; obtain a first trace log of the storage device; and store, into the first memory, a log resulting from appending the obtained random number to the first trace log, as a second trace log.Type: ApplicationFiled: August 19, 2020Publication date: September 23, 2021Applicant: Kioxia CorporationInventors: Ryuji NISHIKUBO, Hirokuni YANO
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Publication number: 20210089234Abstract: According to one embodiment, a memory system includes a nonvolatile memory device to store data; and a memory controller configured to: manage first information allocated to each user and including first management data; perform first processing for an access to the nonvolatile memory device when an access request to the nonvolatile memory device has been received from the user and the first management data is equal to or larger than a first value; and perform second processing for an access to the nonvolatile memory device when the first management data is equal to or larger than a second value.Type: ApplicationFiled: March 13, 2020Publication date: March 25, 2021Applicants: Kioxia Corporation, TOSHIBA INFORMATION SYSTEMS (JAPAN) CORPORATIONInventors: Keisuke YASUI, Ryuji NISHIKUBO, Norio AOYAMA
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Publication number: 20210064345Abstract: A memory system includes a nonvolatile memory and a controller that performs first, second, and third processes on memory cells of the nonvolatile memory. The first process is performed on first memory cells to store a first value therein, such that a highest threshold voltage among the threshold voltages of the first memory cells is set as a first threshold voltage. The second process is performed on second memory cells to store a second value therein, such that a lowest threshold voltage among the threshold voltages of the second memory cells is set as a second threshold voltage higher than the first threshold voltage. The third process performed on third memory cells such that a lowest threshold voltage in the third memory cells is lower than the first threshold voltage, and a highest threshold voltage in the third memory cells is higher than the second threshold voltage.Type: ApplicationFiled: February 26, 2020Publication date: March 4, 2021Inventors: Mel Stychen Sanchez TAN, Aurelien Nam Phong TRAN, Ryuji NISHIKUBO, Norio AOYAMA
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Patent number: 10802917Abstract: According to one embodiment, a memory system includes a nonvolatile memory having a first writing area and a second writing area, and a controller, in which the controller confirms whether processing of preserving data which has been written before shutdown which is not going through a predetermined shutdown procedure is being executed, in the nonvolatile memory, when the controller receives a write command, causes the nonvolatile memory to write data to the first writing area if the processing is not being executed, and causes the nonvolatile memory to write data to the second writing area if the processing is being executed.Type: GrantFiled: September 12, 2018Date of Patent: October 13, 2020Assignee: Toshiba Memory CorporationInventors: Ryuji Nishikubo, Jun Kano
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Patent number: 10599561Abstract: According to one embodiment, a memory system writes data to a first block, and executes a garbage collection when the number of free blocks is not greater than a first threshold value. The memory system calculates a first number which is a ratio of the number of copy destination blocks needed for the garbage collection to the number of blocks to which data designated by a write command is written. The memory system determines whether the first number is greater than a second threshold value when a first command is received from the host, and performs fill-up processing for the first block when the first number is not greater than the second threshold value.Type: GrantFiled: May 8, 2018Date of Patent: March 24, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Ryuji Nishikubo, Hiroki Matsudaira, Norio Aoyama
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Publication number: 20190310917Abstract: According to one embodiment, a memory system includes a nonvolatile memory having a first writing area and a second writing area, and a controller, in which the controller confirms whether processing of preserving data which has been written before shutdown which is not going through a predetermined shutdown procedure is being executed, in the nonvolatile memory, when the controller receives a write command, causes the nonvolatile memory to write data to the first writing area if the processing is not being executed, and causes the nonvolatile memory to write data to the second writing area if the processing is being executed.Type: ApplicationFiled: September 12, 2018Publication date: October 10, 2019Applicant: Toshiba Memory CorporationInventors: Ryuji NISHIKUBO, Jun KANO
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Publication number: 20180253376Abstract: According to one embodiment, a memory system writes data to a first block, and executes a garbage collection when the number of free blocks is not greater than a first threshold value. The memory system calculates a first number which is a ratio of the number of copy destination blocks needed for the garbage collection to the number of blocks to which data designated by a write command is written. The memory system determines whether the first number is greater than a second threshold value when a first command is received from the host, and performs fill-up processing for the first block when the first number is not greater than the second threshold value.Type: ApplicationFiled: May 8, 2018Publication date: September 6, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Ryuji NISHIKUBO, Hiroki Matsudaira, Norio Aoyama
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Patent number: 9996268Abstract: According to one embodiment, a memory system writes data to a first block, and executes a garbage collection when the number of free blocks is not greater than a first threshold value. The memory system calculates a first number which is a ratio of the number of copy destination blocks needed for the garbage collection to the number of blocks to which data designated by a write command is written. The memory system determines whether the first number is greater than a second threshold value when a first command is received from the host, and performs fill-up processing for the first block when the first number is not greater than the second threshold value.Type: GrantFiled: March 11, 2016Date of Patent: June 12, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Ryuji Nishikubo, Hiroki Matsudaira, Norio Aoyama
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Publication number: 20170177235Abstract: According to one embodiment, a memory system writes data to a first block, and executes a garbage collection when the number of free blocks is not greater than a first threshold value. The memory system calculates a first number which is a ratio of the number of copy destination blocks needed for the garbage collection to the number of blocks to which data designated by a write command is written. The memory system determines whether the first number is greater than a second threshold value when a first command is received from the host, and performs fill-up processing for the first block when the first number is not greater than the second threshold value.Type: ApplicationFiled: March 11, 2016Publication date: June 22, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Ryuji NISHIKUBO, Hiroki MATSUDAIRA, Norio AOYAMA
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Patent number: 9465537Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of blocks, and a controller controlling the nonvolatile memory. The controller cyclically executes patrol read, the patrol read including reading data and testing the read data, the read data being data of pages connected to some of word lines in each of the blocks of the nonvolatile memory.Type: GrantFiled: August 21, 2014Date of Patent: October 11, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Ryuji Nishikubo, Hiroki Matsudaira, Norio Aoyama
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Patent number: 9208863Abstract: A controller performs a coding process based on a first frame including data of a plurality of pages connected to first word lines being a predetermined number of consecutive word lines in a block, and performs, when padding data is written to a plurality of pages connected to second word lines being the predetermined number of word lines subsequent to the first word lines, the coding process based on a second frame obtained by excluding the padding data from a frame including data of the pages connected to the second word lines.Type: GrantFiled: August 29, 2014Date of Patent: December 8, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Eiji Yoshihashi, Hiroki Matsudaira, Ryuji Nishikubo, Norio Aoyama
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Publication number: 20150339223Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a plurality of parallel operation elements each having a plurality of physical blocks. The controller drives the plurality of parallel operation elements in parallel. The controller associates each of a plurality of logical blocks with a plurality of physical blocks each belonging to different parallel operation elements. The controller levels, among the plurality of logical blocks, the numbers of Bad blocks included in the plurality of physical blocks being associated with each of the plurality of logical blocks.Type: ApplicationFiled: September 8, 2014Publication date: November 26, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Hiroki MATSUDAIRA, Ryuji NISHIKUBO, Norio AOYAMA
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Publication number: 20150339069Abstract: According to one embodiment, a memory system includes a first memory, a second memory, and a processor. The second memory stores first management information and second management information. The first management information has an information that associates a logical address with a physical address. The second management information has an information which has a volume of valid data in each block included in the first memory. The controller updates the first management information and the second management information. When saving a differential data in the first memory, the controller stores the differential data and the second management information in one page of the first memory. The differential data is a difference between before and after update of the first management information. When restoring the second management information, the controller loads to the second memory the second management information stored in the first memory.Type: ApplicationFiled: September 8, 2014Publication date: November 26, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Ryuji Nishikubo, Hiroki Matsudaira, Norio Aoyama
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Publication number: 20150331625Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of blocks, and a controller controlling the nonvolatile memory. The controller cyclically executes patrol read, the patrol read including reading data and testing the read data, the read data being data of pages connected to some of word lines in each of the blocks of the nonvolatile memory.Type: ApplicationFiled: August 21, 2014Publication date: November 19, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Ryuji NISHIKUBO, Hiroki Matsudaira, Norio Aoyama
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Publication number: 20150332758Abstract: According to an embodiment, a controller performs a coding process based on a first frame including data of a plurality of pages connected to first word lines being a predetermined number of consecutive word lines in a block, and performs, when padding data is written to a plurality of pages connected to second word lines being the predetermined number of word lines subsequent to the first word lines, the coding process based on a second frame obtained by excluding the padding data from a frame including data of the pages connected to the second word lines.Type: ApplicationFiled: August 29, 2014Publication date: November 19, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Eiji Yoshihashi, Hiroki Matsudaira, Ryuji Nishikubo, Norio Aoyama
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Patent number: 9053007Abstract: According to one embodiment, a memory system includes nonvolatile memory and storage unit storing a translation table indicating, by a predetermined management unit, relationships between logical addresses specified by a host and physical addresses in the nonvolatile memory. A memory system of the embodiment includes a controller that when receiving from the host a delete notification indicating a delete area smaller than the management unit specified by a logical address, write a specified data pattern to an area of the nonvolatile memory having a physical address corresponding to the delete area.Type: GrantFiled: September 23, 2011Date of Patent: June 9, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Ryuji Nishikubo
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Patent number: 9047177Abstract: According to one embodiment, a memory system includes a non-volatile memory, a volatile memory, a controller, and a compression/decompression processor. When data transmission is performed through the volatile memory between a host apparatus and the non-volatile memory, the controller updates management information stored in the volatile memory. In addition, the compression/decompression processor compresses the management information in the case where a first condition is satisfied, and decompresses the compressed management information in the case where a second condition is satisfied. The controller stores the compressed management information in the non-volatile memory.Type: GrantFiled: September 11, 2012Date of Patent: June 2, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hiroki Matsudaira, Ryuji Nishikubo