Abstract: In each of a plurality of memory chips in the semiconductor integrated circuit device, an address signal of a defective memory cell in a memory circuit is obtained by a pattern generation tester circuit and a repair analysis circuit, and stored in a replacement storage circuit. The address signal read out of the replacement storage circuit is set to a replacement-repair circuit, and the defective memory cell is replaced with a spare memory cell. The replacement of a defective memory cell with a spare memory cell is allowed even after packaging, so that the yield is increased. The test time is also reduced, as the plurality of memory chips are tested in parallel.

Abstract: A semiconductor module that comprises a plurality of semiconductor chips mounted on a single substrate and which readily diagnoses all the semiconductor chips. A plurality of semiconductor chips are mounted on a single substrate. The semiconductor module is provided with a mode signal pin for receiving a mode signal for requesting performance of a diagnostic operation, as well as with a result output pin for outputting diagnostic results. Further, each of the semiconductor chips is provided with a diagnostic circuit for diagnosing the status of the corresponding semiconductor chip. The semiconductor module is also provided with a diagnosis controller for controlling the diagnostic circuits such that all the semiconductor chips are diagnosed in parallel or serially after a mode signal for requesting a diagnostic operation has been supplied to the mode signal pin.

Abstract: A replacement information storage unit stores additional replacement information determined according to testing carried out during or after assembly. A replacement information addition load unit receives additional replacement information from outside a plurality of memory chips. A replacement data retain unit stores address information corresponding to a defective memory cell found during a fabrication process of a memory chip, and can alter the output address signal according to externally applied additional replacement information.

Abstract: In each of a plurality of memory chips in the semiconductor integrated circuit device, an address signal of a defective memory cell in a memory circuit is obtained by a pattern generation tester circuit and a repair analysis circuit, and stored in a replacement storage circuit. The address signal read out of the replacement storage circuit is set to a replacement-repair circuit, and the defective memory cell is replaced with a spare memory cell. The replacement of a defective memory cell with a spare memory cell is allowed even after packaging, so that the yield is increased. The test time is also reduced, as the plurality of memory chips are tested in parallel.

Abstract: A replacement information storage unit stores additional replacement information determined according to testing carried out during or after assembly. A replacement information addition load unit receives additional replacement information from outside a plurality of memory chips. A replacement data retain unit stores address information corresponding to a defective memory cell found during a fabrication process of a memory chip, and can alter the output address signal according to externally applied additional replacement information.