Abstract: A program power supply of a tester applies a power supply voltage to an IC to be tested. A pattern generator applies a clock signal and a command signal to a BIST circuit of IC. BIST circuit tests memory IC unit and logic IC unit and serially outputs data indicative of test result to a converter of tester. Converter converts the applied serial data to parallel data and applies to computer. As compared with the prior art in which address signal and control signal are applied to IC to be tested, the number of pins necessary for the test can be reduced. Therefore, cost of the test is reduced and efficiency of the test is improved.

Abstract: A repair analysis circuit for redundancy, a redundant method for repairing a redundant, and a semiconductor device that can shorten time for testing defective memory cells, that eliminate the need of failure memories having a huge capacity for storing defective bits to make the testing apparatus inexpensive, and that easily cope with increase and decrease in IO numbers. A large number of IO outputs MOUT are collectively compared with a specified expected value, and as a result resultant judgment information DOUT is outputted to an error information acquiring device 22, and an analyzing device 23 reads table information sequentially from each block to obtain replacing data, and the replacing data are outputted serially to the external tester through the external I/F circuit 24. The redundant memory cell 4a itself can be made to compare with a specified expected value in the same manner as other memory cells 4 or the like.

Abstract: A repair analysis circuit for redundancy, a redundant method for repairing a redundant, and a semiconductor device that can shorten time for testing defective memory cells, that eliminate the need of failure memories having a huge capacity for storing defective bits to make the testing apparatus inexpensive, and that easily cope with increase and decrease in IO numbers. A large number of IO outputs MOUT are collectively compared with a specified expected value, and as a result resultant judgment information DOUT is outputted to an error information acquiring device 22, and an analyzing device 23 reads table information sequentially from each block to obtain replacing data, and the replacing data are outputted serially to the external tester through the external I/F circuit 24. The redundant memory cell 4a itself can be made to compare with a specified expected value in the same manner as other memory cells 4 or the like.

Abstract: A program power supply of a tester applies a power supply voltage to an IC to be tested. A pattern generator applies a clock signal and a command signal to a BIST circuit of IC. BIST circuit tests memory IC unit and logic IC unit and serially outputs data indicative of test result to a converter of tester. Converter converts the applied serial data to parallel data and applies to computer. As compared with the prior art in which address signal and control signal are applied to IC to be tested, the number of pins necessary for the test can be reduced. Therefore, cost of the test is reduced and efficiency of the test is improved.

Abstract: A program power supply of a tester applies a power supply voltage to an IC to be tested. A pattern generator applies a clock signal and a command signal to a BIST circuit of IC. BIST circuit tests memory IC unit and logic IC unit and serially outputs data indicative of test result to a converter of tester. Converter converts the applied serial data to parallel data and applies to computer. As compared with the prior art in which address signal and control signal are applied to IC to be tested, the number of pins necessary for the test can be reduced. Therefore, cost of the test is reduced and efficiency of the test is improved.

Abstract: An IC tester having a plurality of tester pins to be connected to input terminals and output terminals of ICs to be tested comnprises: a common timing generator for generating a common timing which is common to all the tester pins; a dedicated timing generator for generating dedicated timings which are independent of each other and respectively dedicated to tester pin units, each of the tester pin units being composed of at least two of the plurality of tester pins; and a setting device for setting the respective dedicated timings generated by the dedicated timing generator to the tester pins of the corresponding tester pin units, the other tester pins selecting the common timing generated by the common timing generator.

Abstract: A testing device comprises a plurality of pin test portions, each of which is separately provided with a pin pattern controller for controlling the readout of pattern and timing data from pattern and timing memories and a pin instruction memory for storing programs defining the operation procedure of the pin pattern controller. Therefore, the data to be stored in the pattern and timing memories in each of the pin test portions can be in a compressed form, independently of the data to be stored in the pattern and timing memories in the other pin test portions.