Patents by Inventor Ryuji Orita
Ryuji Orita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9678914Abstract: In a method for ejecting a plurality of hot plug slots sharing a power controller, a processor receives a request to eject a plurality of hot plug slots, wherein the plurality of hot plug slots share a power controller and have at least two adapters present. A processor causes an OS to incrementally eject the at least two adapters, wherein ejecting an adapter comprises the OS stopping at least one driver of the adapter, and the OS generating a request to remove power from a hot plug slot. Responsive to a request by the OS to remove power from a hot plug slot, a processor generates a signal that prevents the OS from recognizing the adapter is present in the hot plug slot. Responsive to all device drivers for the at least two adapters being stopped, a processor causes power to be removed from the plurality of hot plug slots.Type: GrantFiled: February 19, 2014Date of Patent: June 13, 2017Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.Inventors: Robert H. Bass, Ryuji Orita, Mehul M. Shah, Timothy M. Wiwel
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Publication number: 20150234768Abstract: In a method for ejecting a plurality of hot plug slots sharing a power controller, a processor receives a request to eject a plurality of hot plug slots, wherein the plurality of hot plug slots share a power controller and have at least two adapters present. A processor causes an OS to incrementally eject the at least two adapters, wherein ejecting an adapter comprises the OS stopping at least one driver of the adapter, and the OS generating a request to remove power from a hot plug slot. Responsive to a request by the OS to remove power from a hot plug slot, a processor generates a signal that prevents the OS from recognizing the adapter is present in the hot plug slot. Responsive to all device drivers for the at least two adapters being stopped, a processor causes power to be removed from the plurality of hot plug slots.Type: ApplicationFiled: February 19, 2014Publication date: August 20, 2015Applicant: International Business Machines CorporationInventors: Robert H. Bass, Ryuji Orita, Mehul M. Shah, Timothy M. Wiwel
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Patent number: 8677160Abstract: Methods, computers, and products for managing power consumption of a computer, the computer including a computer processor and managing power consumption of a computer includes: dynamically during operation of the computer, setting, by an in-band power manager in dependence upon performance metrics of the computer processor, a current performance state (‘p-state’) of the computer processor; and providing, by the in-band power manager to an out-of-band power manager, the current p-state of the computer processor.Type: GrantFiled: July 11, 2012Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventors: Thomas M. Brey, Wesley M. Felter, Sumeet Kochar, Charles R. Lefurgy, Ryuji Orita, Freeman L. Rawson, III, Malcolm S. Ware
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Patent number: 8504875Abstract: A computing device includes a processor, firmware, a hardware component, and a debugging module. The firmware stores error decoding logic particular to the computing device. The hardware component detects an error in the computing device, and responsively issues an interrupt and halts the processor such that the processor cannot execute any more computer-readable code. The debugging module loads the logic from the firmware at reset and executes the logic responsive to the interrupt. The debugging module does not use the processor to execute the logic, the firmware is not part of the debugging module, and the debugging module is not part of the hardware component. The firmware may also store a mapping between registers of the hardware component and field-replaceable hardware units of the computing device, which the debugging module loads at reset and uses when executing the error decoding logic to determine which unit has caused the error.Type: GrantFiled: December 28, 2009Date of Patent: August 6, 2013Assignee: International Business Machines CorporationInventors: Ryuji Orita, Barry A. Kritt, Charles D. Bauman, Sumeet Kochar, Jeremy K. Holland, Karen A. Taylor
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Publication number: 20120284540Abstract: Methods, computers, and products for managing power consumption of a computer, the computer including a computer processor and managing power consumption of a computer includes: dynamically during operation of the computer, setting, by an in-band power manager in dependence upon performance metrics of the computer processor, a current performance state (‘p-state’) of the computer processor; and providing, by the in-band power manager to an out-of-band power manager, the current p-state of the computer processor.Type: ApplicationFiled: July 11, 2012Publication date: November 8, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas M. Brey, Wesley M. Felter, Sumeet Kochar, Charles R. Lefurgy, Ryuji Orita, Freeman L. Rawson, III, Malcom S. Ware
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Patent number: 8307220Abstract: Methods, computers, and products for managing power consumption of a computer, the computer including a computer processor and managing power consumption of a computer includes: dynamically during operation of the computer, setting, by an in-band power manager in dependence upon performance metrics of the computer processor, a current performance state (‘p-state’) of the computer processor; and providing, by the in-band power manager to an out-of-band power manager, the current p-state of the computer processor.Type: GrantFiled: June 25, 2008Date of Patent: November 6, 2012Assignee: International Business Machines CorporationInventors: Thomas M. Brey, Wesley M. Felter, Sumeet Kochar, Charles R. Lefurgy, Ryuji Orita, Freeman L. Rawson, III, Malcolm S. Ware
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Patent number: 8103884Abstract: Methods and products for managing power consumption of a computer and computers for which power consumption is managed. The computer includes the computer including a computer processor and embodiments of the present invention include providing, by an in-band power manger to an out-of-band power manager, a proposed performance state (‘p-state’) for the computer processor; determining, by the out-of-band power manager, in dependence upon a power setpoint and currently-measured operating metrics of the computer processor, whether to approve the proposed p-state; and if the out-of-band power manager approves the proposed p-state, setting operating parameters of the computer processor according to the approved p-state.Type: GrantFiled: June 25, 2008Date of Patent: January 24, 2012Assignee: International Business Machines CorporationInventors: Thomas M. Brey, Wesley M. Felter, Sumeet Kochar, Charles R. Lefurgy, Ryuji Orita, Freeman L. Rawson, III, Malcolm S. Ware
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Patent number: 8041936Abstract: The last value of an element of a computing system is continually stored within a first register. The element is cleared during any restart or reset of the computing system. The last value is relevant to debugging of the computing system when the computing system fails to perform as expected and/or as desired. Upon receiving an instruction to reset the computing system via a first reset signal corresponding to pressing of a reset button or a second reset signal corresponding to a baseboard management controller issuing a reset command, the last value of the element as stored within the first register is copied to a second register. The computing system is then reset. The last value of the element as stored within the second register persists within the second register during this type of reset, but is cleared during any other reset or restart of the computing system.Type: GrantFiled: October 28, 2007Date of Patent: October 18, 2011Assignee: International Business Machines CorporationInventors: Ryuji Orita, Mark A. Brandyberry, Mehul M. Shah, Sean P. Brogan
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Publication number: 20110161736Abstract: A computing device includes a processor, firmware, a hardware component, and a debugging module. The firmware stores error decoding logic particular to the computing device. The hardware component detects an error in the computing device, and responsively issues an interrupt and halts the processor such that the processor cannot execute any more computer-readable code. The debugging module loads the logic from the firmware at reset and executes the logic responsive to the interrupt. The debugging module does not use the processor to execute the logic, the firmware is not part of the debugging module, and the debugging module is not part of the hardware component. The firmware may also store a mapping between registers of the hardware component and field-replaceable hardware units of the computing device, which the debugging module loads at reset and uses when executing the error decoding logic to determine which unit has caused the error.Type: ApplicationFiled: December 28, 2009Publication date: June 30, 2011Inventors: Ryuji Orita, Barry A. Kritt, Charles D. Bauman, Sumeet Kochar, Jeremy K. Holland, Karen A. Taylor
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Patent number: 7793291Abstract: A method and apparatus are provided for thermal management of a multiprocessor computer system. The temperatures of the various processors within a multiprocessor system are monitored. When a processor is identified as overheated, a dummy process will be assigned to it, causing all other processes to be put on hold, thereby reducing the heat output of that processor. When the temperature of the processor lowers below another predetermined value, then the dummy process is terminated.Type: GrantFiled: December 22, 2004Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Susumi Arai, Ryuji Orita
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Patent number: 7694055Abstract: Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of the currently idle processors for processing. Determining which processors are currently idle can be accomplished by monitoring each processor to determine whether it has entered an idle state. When a processor has entered an idle state, it is thus determined that the processor is currently idle. Where just one processor is currently idle, an interrupt is directed to this processor. Where more than one processor is currently idle, one of these processors is selected to which to deliver an interrupt, such as in a round-robin manner. Where no processor is currently idle, then one of the processors is selected to which to deliver an interrupt.Type: GrantFiled: October 15, 2005Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventors: Ryuji Orita, Susumu Arai, Brian D. Allison, Patrick M. Bland
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Publication number: 20100064080Abstract: The present disclosure is directed to a method for balancing latency versus bandwidth trade-offs in packet transmission utilizing PCI-Express. The method may comprise identifying at least one system element along a path of a packet to be transmitted; determining and storing an optimum payload size for each one of the at least one system element; configuring a Max Payload Size parameter for each one of the at least one system element, wherein the Max Payload Size parameter is configured based on the optimum payload size for each one of the at least one system element.Type: ApplicationFiled: September 11, 2008Publication date: March 11, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mehul Shah, Ryuji Orita, Sandra D. Rhodes
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Publication number: 20090327764Abstract: Methods, computers, and products for managing power consumption of a computer, the computer including a computer processor and managing power consumption of a computer includes: dynamically during operation of the computer, setting, by an in-band power manager in dependence upon performance metrics of the computer processor, a current performance state (‘p-state’) of the computer processor; and providing, by the in-band power manager to an out-of-band power manager, the current p-state of the computer processor.Type: ApplicationFiled: June 25, 2008Publication date: December 31, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas M. Brey, Wesley M. Felter, Sumeet Kochar, Charles R. Lefurgy, Ryuji Orita, Freeman L. Rawson, III, Malcolm S. Ware
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Publication number: 20090327765Abstract: Methods and products for managing power consumption of a computer and computers for which power consumption is managed. The computer includes the computer including a computer processor and embodiments of the present invention include providing, by an in-band power manger to an out-of-band power manager, a proposed performance state (‘p-state’) for the computer processor; determining, by the out-of-band power manager, in dependence upon a power setpoint and currently-measured operating metrics of the computer processor, whether to approve the proposed p-state; and if the out-of-band power manager approves the proposed p-state, setting operating parameters of the computer processor according to the approved p-state.Type: ApplicationFiled: June 25, 2008Publication date: December 31, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas M. Brey, Wesley M. Felter, Sumeet Kochar, Charles R. Lefurgy, Ryuji Orita, Freeman L. Rawson, III, Malcolm S. Ware
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Publication number: 20090113194Abstract: The last value of an element of a computing system is continually stored within a first register. The element is cleared during any restart or reset of the computing system. The last value is relevant to debugging of the computing system when the computing system fails to perform as expected and/or as desired. Upon receiving an instruction to reset the computing system via a first reset signal corresponding to pressing of a reset button or a second reset signal corresponding to a baseboard management controller issuing a reset command, the last value of the element as stored within the first register is copied to a second register. The computing system is then reset. The last value of the element as stored within the second register persists within the second register during this type of reset, but is cleared during any other reset or restart of the computing system.Type: ApplicationFiled: October 28, 2007Publication date: April 30, 2009Inventors: Ryuji Orita, Mark A. Brandyberry, Mehul M. Shah, Sean P. Brogan
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Patent number: 7447934Abstract: A method, system, and program product for recovering from a bus error in a computer system having a hot plug interface. In accordance with the method of the present invention, an operating system transparent interrupt, such as a system management interrupt, is generated in response to a bus error. Responsive to the operating system transparent interrupt, the hot pluggable bus is scanned and a device associated with the error is identified by an interrupt handler invoked by the interrupt. Finally, a hot plug configuration manager, such as an advanced configuration and power interface is utilized to remove the identified device from system operations without having to restart the system.Type: GrantFiled: June 27, 2005Date of Patent: November 4, 2008Assignee: International Business Machines CorporationInventors: Shiva R. Dasari, Sudhir Dhawan, Ryuji Orita, Wingcheung T. Tam
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Publication number: 20070239972Abstract: Internal timestamp counter instructions are instead processed in reference to an external counter. A processor receives an instruction to access an internal timestamp counter of the processor, such as from software code containing the instruction that is currently being executed by the processor. The processor processes the instruction, however, in reference to an external counter apart from the processor, instead of in reference to the internal timestamp counter. The code is thus unaware that the instruction is being processed in reference to the external counter instead of in reference to the internal timestamp counter, and does not have to be rewritten or recompiled to take advantage of the external counter. That is, the code still has instructions that are intended to access the internal timestamp counter, and these instructions are instead executed in reference to an external counter, such as a phase-locked loop (PLL) clock of a Northbridge controller.Type: ApplicationFiled: April 8, 2006Publication date: October 11, 2007Inventors: Ryuji Orita, Michael Turner
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Publication number: 20070239917Abstract: Interrupts are routed within a multiple-processor system, such as a single computing device having multiple processors. Such a computerized system includes a number of processors and a mechanism. Each processor is capable of processing an interrupt. The mechanism, such as a Southbridge controller, receives the interrupt and routes it to a selected processor. The selected processor processes the interrupt via entry into a mode related to the interrupt. The interrupt may be a system management interrupt (SMI), and the mode a system management mode (SMM). The other processors operate normally and are not affected by processing of the interrupt, and do not have to enter the mode. These other processors can continue executing code as before, and may receive and process other types of interrupts. The system may include another mechanism, such as a complex programmable logic device (CPLD), specifying the selected processor.Type: ApplicationFiled: December 9, 2005Publication date: October 11, 2007Inventors: Ryuji Orita, Mehul Shah, Sumeet Kochar
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Publication number: 20070088888Abstract: Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of the currently idle processors for processing. Determining which processors are currently idle can be accomplished by monitoring each processor to determine whether it has entered an idle state. When a processor has entered an idle state, it is thus determined that the processor is currently idle. Where just one processor is currently idle, an interrupt is directed to this processor. Where more than one processor is currently idle, one of these processors is selected to which to deliver an interrupt, such as in a round-robin manner. Where no processor is currently idle, then one of the processors is selected to which to deliver an interrupt.Type: ApplicationFiled: October 15, 2005Publication date: April 19, 2007Inventors: Ryuji Orita, Susumu Arai, Brian Allison, Patrick Bland
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Publication number: 20070011500Abstract: A method, system, and program product for recovering from a bus error in a computer system having a hot plug interface. In accordance with the method of the present invention, an operating system transparent interrupt, such as a system management interrupt, is generated in response to a bus error. Responsive to the operating system transparent interrupt, the hot pluggable bus is scanned and a device associated with the error is identified by an interrupt handler invoked by the interrupt. Finally, a hot plug configuration manager, such as an advanced configuration and power interface is utilized to remove the identified device from system operations without having to restart the system.Type: ApplicationFiled: June 27, 2005Publication date: January 11, 2007Applicant: International Business Machines CorporationInventors: Shiva Dasari, Sudhir Dhawan, Ryuji Orita, Wingcheung Tam